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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 1035.40KB

  • 101頁

  • Altera   Altera

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Chapter 5: DC and Switching Characteristics
Timing Model and Specifications
5鈥?1
f
For more explanations and descriptions about each internal timing microparameters
symbol, refer to the
Understanding Timing in MAX II Devices
chapter in the
MAX II
Device Handbook.
Table 5鈥?5.
LE Internal Timing Microparameters
鈥? Speed
Grade
Symbol
t
LUT
t
COMB
t
CLR
t
PRE
t
SU
t
H
t
CO
t
CLKHL
t
C
Parameter
LE combinational LUT
delay
Combinational path delay
LE register clear delay
LE register preset delay
LE register setup time
before clock
LE register hold time after
clock
LE register clock-to-output
delay
Minimum clock high or low
time
Register control delay
Min
鈥?/div>
鈥?/div>
238
238
208
0
鈥?/div>
166
鈥?/div>
Max
571
147
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
235
鈥?/div>
857
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
309
309
271
0
鈥?/div>
216
鈥?/div>
Max
742
192
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
305
鈥?/div>
1,114
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
381
381
333
0
鈥?/div>
266
鈥?/div>
Max
914
236
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
376
鈥?/div>
1,372
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
401
401
260
0
鈥?/div>
253
鈥?/div>
Max
1,215
243
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
380
鈥?/div>
1,356
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
541
541
319
0
鈥?/div>
335
鈥?/div>
Max
2,247
305
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
489
鈥?/div>
1,722
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
Table 5鈥?6.
IOE Internal Timing Microparameters (Part 1 of 2)
鈥? Speed
Grade
Symbol
t
FASTIO
t
IN
t
GLOB
(1)
Parameter
Data output delay from
adjacent LE to I/O block
I/O input pad and buffer
delay
I/O input pad and buffer
delay used as global signal
pin
Internally generated output
enable delay
Input routing delay
Output delay buffer and pad
delay
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
159
708
1,519
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
207
920
1,974
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
254
1,132
2,430
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
170
907
2,261
鈥? Speed
Grade
Min
鈥?/div>
鈥?/div>
鈥?/div>
Max
348
970
2,670
Unit
ps
ps
ps
t
IOE
t
DL
t
OD
(2)
鈥?/div>
鈥?/div>
鈥?/div>
354
224
1,064
鈥?/div>
鈥?/div>
鈥?/div>
374
291
1,383
鈥?/div>
鈥?/div>
鈥?/div>
460
358
1,702
鈥?/div>
鈥?/div>
鈥?/div>
530
318
1,319
鈥?/div>
鈥?/div>
鈥?/div>
966
410
1,526
ps
ps
ps
漏 Novermber 2008 Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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