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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

5鈥?
Chapter 5: DC and Switching Characteristics
Operating Conditions
Table 5鈥?.
MAX II Device DC Electrical Characteristics
(Note 1)
(Part 2 of 2)
Symbol
I
PULLUP
Parameter
I/O pin pull-up resistor
current when I/O is
unprogrammed
Input capacitance for
user I/O pin
Input capacitance for
dual-purpose
GCLK/user I/O pin
Conditions
鈥?/div>
Minimum
鈥?/div>
Typical
鈥?/div>
Maximum
300
Unit
碌A(chǔ)
C
IO
C
GCLK
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
8
8
pF
pF
Notes to
Table 5鈥?:
(1) Typical values are for T
A
= 25 擄C, V
CCINT
= 3.3 or 2.5 V, and V
CCIO
= 1.5 V, 1.8 V, 2.5 V, or 3.3 V.
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all V
CCIO
settings (3.3, 2.5,
1.8, and 1.5 V).
(3) V
I
= ground, no load, no toggling inputs.
(4) This value applies to commercial and industrial range devices. For extended temperature range devices, the V
SCHMITT
typical value is
300 mV for V
CCIO
= 3.3 V and 120 mV for V
CCIO
= 2.5 V.
(5) The
TCK
input is susceptible to high pulse glitches when the input signal fall time is greater than 200 ns for all I/O standards.
(6) This is a peak current value with a maximum duration of t
CONFIG
time.
(7) Pin pull-up resistance values will lower if an external source drives the pin higher than V
CCIO
.
MAX II Device Handbook
漏 Novermber 2008 Altera Corporation

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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