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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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上傳產(chǎn)品規(guī)格書

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5鈥?
Chapter 5: DC and Switching Characteristics
Operating Conditions
Recommended Operating Conditions
Table 5鈥?
shows the MAX II device family recommended operating conditions.
Table 5鈥?.
MAX II Device Recommended Operating Conditions
Symbol
V
CCINT
(1)
Parameter
3.3-V supply voltage for internal logic and
ISP
2.5-V supply voltage for internal logic and
ISP
1.8-V supply voltage for internal logic and
ISP
V
CCIO
(1)
Supply voltage for I/O buffers, 3.3-V
operation
Supply voltage for I/O buffers, 2.5-V
operation
Supply voltage for I/O buffers, 1.8-V
operation
Supply voltage for I/O buffers, 1.5-V
operation
V
I
V
O
T
J
Input voltage
Output voltage
Operating junction temperature
Conditions
MAX II devices
MAX II devices
MAX IIG and MAX IIZ
devices
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
(2), (3), (4)
鈥?/div>
Commercial range
(5)
Industrial range
Extended range
(6)
Notes to
Table 5鈥?:
(1) MAX II device in-system programming and/or user flash memory (UFM) programming via JTAG or logic array is not guaranteed outside the
recommended operating conditions (for example, if brown-out occurs in the system during a potential write/program sequence to the UFM,
users are recommended to read back UFM contents and verify against the intended write data).
(2) Minimum DC input is 鈥?.5 V. During transitions, the inputs may undershoot to 鈥?.0 V for input currents less than 100 mA and periods shorter
than 20 ns.
(3) During transitions, the inputs may overshoot to the voltages shown in the following table based upon input duty cycle. The DC case is equivalent
to 100% duty cycle. For more information about 5.0-V tolerance, refer to the
Using MAX II Devices in Multi-Voltage Systems
chapter in the
MAX
II Device Handbook.
V
IN
Max. Duty Cycle
4.0 V 100% (DC)
4.1
90%
4.2
50%
4.3
30%
4.4
17%
4.5
10%
(4) All pins, including clock, I/O, and JTAG pins, may be driven before V
CCINT
and V
CCIO
are powered.
(5) MAX IIZ devices are only available in the commercial temperature range.
(6) For the extended temperature range of 100 to 125潞 C, MAX II UFM programming (erase/write) is only supported via the JTAG interface. UFM
programming via the logic array interface is not guaranteed in this range.
Minimum
3.00
2.375
1.71
3.00
2.375
1.71
1.425
鈥?.5
0
0
鈥?0
鈥?0
Maximum
3.60
2.625
1.89
3.60
2.625
1.89
1.575
4.0
V
CCIO
85
100
125
Unit
V
V
V
V
V
V
V
V
V
擄C
擄C
擄C
MAX II Device Handbook
漏 Novermber 2008 Altera Corporation

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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