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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁(yè)

  • Altera   Altera

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Chapter 4: Hot Socketing and Power-On Reset in MAX II Devices
Power-On Reset Circuitry
4鈥?
Figure 4鈥?.
Power-Up Characteristics for MAX II, MAX IIG, and MAX IIZ Devices
(Note 1), (2)
V
CCINT
3.3 V
2.5 V
Device Resets
the
SRAM
and
Tri-States I/O Pins
MAX II Device
Approximate Voltage
for
SRAM
Download
Start
1.7 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
Tri-State
V
CCINT
3.3 V
MAX IIG Device
Approximate Voltage
for
SRAM
Download
Start
1.8 V
1.55 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
Device Resets
the
SRAM
and
Tri-States I/O Pins
Tri-State
V
CCINT
3.3 V
MAX IIZ Device
Approximate Voltage
for
SRAM
Download
Start
1.8 V
1.55 V
1.4 V
t
CONFIG
0V
Tri-State
User Mode
Operation
V
CCINT
must be powered down
to 0 V if the V
CCINT
dips below this level
minimum 10
碌s
t
CONFIG
User Mode
Operation
Tri-State
Notes to
Figure 4鈥?:
(1) Time scale is relative.
(2)
Figure 4鈥?
assumes all V
CCIO
banks power up simultaneously with the V
CCINT
profile shown. If not, t
CONFIG
stretches out until all V
CCIO
banks are powered.
1
After SRAM configuration, all registers in the device are cleared and released into
user function before I/O tri-states are released. To release clears after tri-states are
released, use the
DEV_CLRn
pin option. To hold the tri-states beyond the power-up
configuration time, use the
DEV_OE
pin option.
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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