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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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Chapter 3: JTAG and In-System Programmability
In System Programmability
3鈥?
IEEE 1532 Support
The JTAG circuitry and ISP instruction set in MAX II devices is compliant to the IEEE
1532-2002 programming specification. This provides industry-standard hardware and
software for in-system programming among multiple vendor programmable logic
devices (PLDs) in a JTAG chain.
The MAX II 1532 BSDL files will be released on the Altera website when available.
Jam Standard Test and Programming Language (STAPL)
The Jam STAPL JEDEC standard, JESD71, can be used to program MAX II devices
with in-circuit testers, PCs, or embedded processors. The Jam byte code is also
supported for MAX II devices. These software programming protocols provide a
compact embedded solution for programming MAX II devices.
f
For more information, refer to the
Using Jam STAPL for ISP via an Embedded Processor
chapter in the
MAX II Device Handbook.
Programming Sequence
During in-system programming, 1532 instructions, addresses, and data are shifted
into the MAX II device through the
TDI
input pin. Data is shifted out through the
TDO
output pin and compared against the expected data. Programming a pattern into the
device requires the following six ISP steps. A stand-alone verification of a
programmed pattern involves only stages 1, 2, 5, and 6. These steps are automatically
executed by third-party programmers, the Quartus II software, or the Jam STAPL and
Jam Byte-Code Players.
1.
Enter ISP鈥擳he
enter ISP stage ensures that the I/O pins transition smoothly from
user mode to ISP mode.
2.
Check ID鈥擝efore
any program or verify process, the silicon ID is checked. The
time required to read this silicon ID is relatively small compared to the overall
programming time.
3.
Sector Erase鈥擡rasing
the device in-system involves shifting in the instruction to
erase the device and applying an erase pulse(s). The erase pulse is automatically
generated internally by waiting in the run/test/idle state for the specified erase
pulse time of 500 ms for the CFM block and 500 ms for each sector of the UFM
block.
4.
Program鈥擯rogramming
the device in-system involves shifting in the address,
data, and program instruction and generating the program pulse to program the
flash cells. The program pulse is automatically generated internally by waiting in
the run/test/idle state for the specified program pulse time of 75 碌s. This process
is repeated for each address in the CFM and UFM blocks.
5.
Verify鈥擵erifying
a MAX II device in-system involves shifting in addresses,
applying the verify instruction to generate the read pulse, and shifting out the data
for comparison. This process is repeated for each CFM and UFM address.
6.
Exit ISP鈥擜n
exit ISP stage ensures that the I/O pins transition smoothly from ISP
mode to user mode.
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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