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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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Chapter 3: JTAG and In-System Programmability
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
3鈥?
Table 3鈥?.
32-Bit MAX II Device IDCODE (Part 2 of 2)
Binary IDCODE (32 Bits)
(1)
Device
EPM240Z
EPM570Z
Notes to
Table 3鈥?:
(1) The most significant bit (MSB) is on the left.
(2) The
IDCODE鈥檚
least significant bit (LSB) is always 1.
Version
(4 Bits)
0000
0000
Part Number
0010 0000 1010 0101
0010 0000 1010 0110
Manufacturer
Identity (11 Bits)
000 0110 1110
000 0110 1110
LSB
(1 Bit)
(2)
1
1
HEX IDCODE
0x020A50DD
0x020A60DD
f
For JTAG AC characteristics, refer to the
DC and Switching Characteristics
chapter in
the
MAX II Device Handbook.
For more information about JTAG BST, refer to the
IEEE 1149.1 (JTAG) Boundary-Scan
Testing for MAX II Devices
chapter in the
MAX II Device Handbook.
f
JTAG Block
The MAX II JTAG block feature allows you to access the JTAG TAP and state signals
when either the
USER0
or
USER1
instruction is issued to the JTAG TAP. The
USER0
and
USER1
instructions bring the JTAG boundary-scan chain (TDI) through the user
logic instead of the MAX II device鈥檚 boundary-scan cells. Each
USER
instruction
allows for one unique user-defined JTAG chain into the logic array.
Parallel Flash Loader
The JTAG block ability to interface JTAG to non-JTAG devices is ideal for general-
purpose flash memory devices (such as Intel- or Fujitsu-based devices) that require
programming during in-circuit test. The flash memory devices can be used for FPGA
configuration or be part of system memory. In many cases, the MAX II device is
already connected to these devices as the configuration control logic between the
FPGA and the flash device. Unlike ISP-capable CPLD devices, bulk flash devices do
not have JTAG TAP pins or connections. For small flash devices, it is common to use
the serial JTAG scan chain of a connected device to program the non-JTAG flash
device. This is slow and inefficient in most cases and impractical for large parallel
flash devices. Using the MAX II device鈥檚 JTAG block as a parallel flash loader, with
the Quartus II software, to program and verify flash contents provides a fast and cost-
effective means of in-circuit programming during test.
Figure 3鈥?
shows MAX II
being used as a parallel flash loader.
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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