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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 1035.40KB

  • 101頁(yè)

  • Altera   Altera

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3. JTAG and In-System Programmability
MII51003-1.6
Introduction
This chapter discusses how to use the IEEE Standard 1149.1 Boundary-Scan Test (BST)
circuitry in MAX II devices and includes the following sections:
鈻?/div>
鈻?/div>
鈥淚EEE Std. 1149.1 (JTAG) Boundary-Scan Support鈥?on page 3鈥?
鈥淚n System Programmability鈥?on page 3鈥?
IEEE Std. 1149.1 (JTAG) Boundary-Scan Support
All MAX
廬
II devices provide Joint Test Action Group (JTAG) boundary-scan test (BST)
circuitry that complies with the IEEE Std. 1149.1-2001 specification. JTAG boundary-
scan testing can only be performed at any time after V
CCINT
and all V
CCIO
banks have
been fully powered and a t
CONFIG
amount of time has passed. MAX II devices can also
use the JTAG port for in-system programming together with either the Quartus
廬
II
software or hardware using Programming Object Files (.pof), JamTM Standard Test
and Programming Language (STAPL) Files (.jam), or Jam Byte-Code Files (.jbc).
The JTAG pins support 1.5-V, 1.8-V, 2.5-V, or 3.3-V I/O standards. The supported
voltage level and standard are determined by the V
CCIO
of the bank where it resides.
The dedicated JTAG pins reside in Bank 1 of all MAX II devices.
MAX II devices support the JTAG instructions shown in
Table 3鈥?.
Table 3鈥?.
MAX II JTAG Instructions (Part 1 of 2)
JTAG Instruction
SAMPLE/PRELOAD
Instruction Code
00 0000 0101
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial data
pattern to be output at the device pins.
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
Selects the 32-bit
USERCODE
register and places it between the
TDI
and
TDO
pins, allowing the
USERCODE
to be serially shifted
out of
TDO.
This register defaults to all 1鈥檚 if not specified in the
Quartus II software.
Selects the
IDCODE
register and places it between
TDI
and
TDO,
allowing the
IDCODE
to be serially shifted out of
TDO.
Places the 1-bit bypass register between the
TDI
and
TDO
pins,
which allows the boundary scan test data to pass synchronously
through selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
EXTEST
(1)
00 0000 1111
BYPASS
11 1111 1111
USERCODE
00 0000 0111
IDCODE
HIGHZ
(1)
00 0000 0110
00 0000 1011
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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