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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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2鈥?2
Chapter 2: MAX II Architecture
Referenced Documents
Connect
VCCIO
pins to either a 1.5-V, 1.8 V, 2.5-V, or 3.3-V power supply, depending
on the output requirements. The output levels are compatible with systems of the
same voltage as the power supply (that is, when
VCCIO
pins are connected to a 1.5-V
power supply, the output levels are compatible with 1.5-V systems). When
VCCIO
pins are connected to a 3.3-V power supply, the output high is 3.3 V and is compatible
with 3.3-V or 5.0-V systems.
Table 2鈥?
summarizes MAX II MultiVolt I/O support.
Table 2鈥?.
MAX II MultiVolt I/O Support
(Note 1)
Input Signal
VCCIO (V)
1.5
1.8
2.5
3.3
1.5 V
v
v
鈥?/div>
鈥?/div>
1.8 V
v
v
鈥?/div>
鈥?/div>
2.5 V
v
v
v
v
(4)
3.3 V
v
v
v
v
5.0 V
鈥?/div>
鈥?/div>
鈥?/div>
v
(5)
1.5 V
v
v
(2)
v
(3)
v
(6)
1.8 V
鈥?/div>
v
v
(3)
v
(6)
Output Signal
2.5 V
鈥?/div>
鈥?/div>
v
v
(6)
3.3 V
鈥?/div>
鈥?/div>
鈥?/div>
v
5.0 V
鈥?/div>
鈥?/div>
鈥?/div>
v
(7)
Notes to
Table 2鈥?:
(1) To drive inputs higher than V
CCIO
but less than 4.0 V including the overshoot, disable the I/O clamp diode. However, to drive 5.0-V inputs to the
device, enable the I/O clamp diode to prevent V
I
from rising above 4.0 V.
(2) When V
CCIO
= 1.8 V, a MAX II device can drive a 1.5-V device with 1.8-V tolerant inputs.
(3) When V
CCIO
= 2.5 V, a MAX II device can drive a 1.5-V or 1.8-V device with 2.5-V tolerant inputs.
(4) When V
CCIO
= 3.3 V and a 2.5-V input signal feeds an input pin, the VCCIO supply current will be slightly larger than expected.
(5) MAX II devices can be 5.0-V tolerant with the use of an external resistor and the internal I/O clamp diode on the EPM1270 and EPM2210
devices.
(6) When V
CCIO
= 3.3 V, a MAX II device can drive a 1.5-V, 1.8-V, or 2.5-V device with 3.3-V tolerant inputs.
(7) When V
CCIO
= 3.3 V, a MAX II device can drive a device with 5.0-V TTL inputs but not 5.0-V CMOS inputs. In the case of 5.0-V CMOS, open-
drain setting with internal I/O clamp diode (available only on EPM1270 and EPM2210 devices) and external resistor is required.
f
For information about output pin source and sink current guidelines, refer to the
AN
428: MAX II CPLD Design Guidelines.
Referenced Documents
This chapter referenced the following documents:
鈻?/div>
鈻?/div>
鈻?/div>
AN 428: MAX II CPLD Design Guidelines
DC and Switching Characteristics
chapter in the
MAX II Device Handbook
Hot Socketing and Power-On Reset in MAX II Devices
chapter in the
MAX II Device
Handbook
Using User Flash Memory in MAX II Devices
chapter in the
MAX II Device Handbook
鈻?/div>
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5 產品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD(復雜可編程邏輯器件)

  • MAX® II

  • 系統(tǒng)內可編程

  • 4.7ns

  • 2.5V,3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP(14x14)

  • 托盤

  • 544-1146

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