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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 1035.40KB

  • 101頁

  • Altera   Altera

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Chapter 2: MAX II Architecture
User Flash Memory Block
2鈥?9
鈻?/div>
鈻?/div>
Auto-increment addressing
Serial interface to logic array with programmable interface
Figure 2鈥?5.
UFM Block and Interface Signals
UFM Block
PROGRAM
ERASE
Program
Erase
Control
OSC
_4
:
RTP_BUSY
BUSY
OSC_ENA
OSC
9
ARCLK
UFM Sector 1
UFM Sector 0
Address
Register
16
ARSHFT
16
ARDin
DRDin
DRCLK
DRSHFT
Data Register
DRDout
UFM Storage
Each device stores up to 8,192 bits of data in the UFM block.
Table 2鈥?
shows the data
size, sector, and address sizes for the UFM block.
Table 2鈥?.
UFM Array Size
Device
EPM240
EPM570
EPM1270
EPM2210
Total Bits
8,192
Sectors
2
(4,096 bits/sector)
Address Bits
9
Data Width
16
There are 512 locations with 9-bit addressing ranging from
000h
to
1FFh.
Sector 0
address space is
000h
to
0FFh
and Sector 1 address space is from
100h
to
1FFh.
The
data width is up to 16 bits of data. The Quartus II software automatically creates logic
to accommodate smaller read or program data widths. Erasure of the UFM involves
individual sector erasing (that is, one erase of sector 0 and one erase of sector 1 is
required to erase the entire UFM block). Since sector erase is required before a
program or write, having two sectors enables a sector size of data to be left untouched
while the other sector is erased and programmed with new data.
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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