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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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2鈥?8
Chapter 2: MAX II Architecture
User Flash Memory Block
Figure 2鈥?4.
Global Clock Network
(Note 1)
I/O Block Region
LAB Column
clock[3..0]
4
4
4
4
4
4
4
4
LAB Column
clock[3..0]
I/O Block Region
UFM Block (2)
CFM Block
I/O Block Region
Notes to
Figure 2鈥?4:
(1) LAB column clocks in I/O block regions provide high fan-out output enable signals.
(2) LAB column clocks drive to the UFM block.
User Flash Memory Block
MAX II devices feature a single UFM block, which can be used like a serial EEPROM
for storing non-volatile information up to 8,192 bits. The UFM block connects to the
logic array through the MultiTrack interconnect, allowing any LE to interface to the
UFM block.
Figure 2鈥?5
shows the UFM block and interface signals. The logic array is
used to create customer interface or protocol logic to interface the UFM block data
outside of the device. The UFM block offers the following features:
鈻?/div>
鈻?/div>
鈻?/div>
鈻?/div>
Non-volatile storage up to 16-bit wide and 8,192 total bits
Two sectors for partitioned sector erase
Built-in internal oscillator that optionally drives logic array
Program, erase, and busy signals
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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