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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 1035.40KB

  • 101頁

  • Altera   Altera

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2鈥?0
Chapter 2: MAX II Architecture
Logic Elements
The other two LUTs use the data1 and data2 signals to generate two possible carry-out
signals: one for a carry of 1 and the other for a carry of 0. The
carry-in0
signal acts
as the carry-select for the
carry-out0
output and
carry-in1
acts as the carry-
select for the
carry-out1
output. LEs in arithmetic mode can drive out registered
and unregistered versions of the LUT output.
The dynamic arithmetic mode also offers clock enable, counter enable, synchronous
up/down control, synchronous clear, synchronous load, and dynamic
adder/subtractor options. The LAB local interconnect data inputs generate the
counter enable and synchronous up/down control signals. The synchronous clear
and synchronous load options are LAB-wide signals that affect all registers in the
LAB. The Quartus II software automatically places any registers that are not used by
the counter into other LABs. The addnsub LAB-wide signal controls whether the LE
acts as an adder or subtractor.
Figure 2鈥?.
LE in Dynamic Arithmetic Mode
LAB Carry-In
Carry-In0
Carry-In1
addnsub
(LAB
Wide)
(1)
sload
sclear
(LAB
Wide)
(LAB
Wide)
Register chain
connection
aload
(LAB
Wide)
data1
data2
data3
LUT
ALD/PRE
ADATA Q
D
ENA
CLRN
Row, column, and
direct link routing
Row, column, and
direct link routing
LUT
LUT
clock (LAB
Wide)
ena (LAB
Wide)
aclr (LAB
Wide)
Local routing
LUT
LUT chain
connection
Register
chain output
Register Feedback
Carry-Out0 Carry-Out1
Note to
Figure 2鈥?:
(1) The
addnsub
signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between LEs in
dynamic arithmetic mode. The carry-select chain uses the redundant carry calculation
to increase the speed of carry functions. The LE is configured to calculate outputs for a
possible carry-in of 0 and carry-in of 1 in parallel. The
carry-in0
and
carry-in1
signals from a lower-order bit feed forward into the higher-order bit via the parallel
carry chain and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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