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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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Chapter 2: MAX II Architecture
Logic Elements
2鈥?
Figure 2鈥?.
MAX II LE
Register chain
routing from
previous LE
LAB-wide
Register Bypass
Synchronous
Load
LAB-wide
Packed
Synchronous
Register
Select
Clear
LAB Carry-In
addnsub
Carry-In1
Carry-In0
Programmable
Register
LUT chain
routing to next LE
Row, column,
and DirectLink
routing
data1
data2
data3
data4
ENA
CLRN
Look-Up
Table
(LUT)
Carry
Chain
Synchronous
Load and
Clear Logic
PRN/ALD
D
Q
ADATA
Row, column,
and DirectLink
routing
labclr1
labclr2
labpre/aload
Chip-Wide
Reset (DEV_CLRn)
Asynchronous
Clear/Preset/
Load Logic
Local routing
Clock and
Clock Enable
Select
labclk1
labclk2
labclkena1
labclkena2
Register
Feedback
Register chain
output
Carry-Out0
Carry-Out1
LAB Carry-Out
Each LE鈥檚 programmable register can be configured for D, T, JK, or SR operation. Each
register has data, true asynchronous load data, clock, clock enable, clear, and
asynchronous load/preset inputs. Global signals, general-purpose I/O pins, or any
LE can drive the register鈥檚 clock and clear control signals. Either general-purpose I/O
pins or LEs can drive the clock enable, preset, asynchronous load, and asynchronous
data. The asynchronous load data input comes from the data3 input of the LE. For
combinational functions, the LUT output bypasses the register and drives directly to
the LE outputs.
Each LE has three outputs that drive the local, row, and column routing resources. The
LUT or register output can drive these three outputs independently. Two LE outputs
drive column or row and DirectLink routing connections and one drives local
interconnect resources. This allows the LUT to drive one output while the register
drives another output. This register packing feature improves device utilization
because the device can use the register and the LUT for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
LE so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The LE can also drive out registered and
unregistered versions of the LUT output.
漏 October 2008
Altera Corporation
MAX II Device Handbook

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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