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EPM240T100C5 Datasheet

  • EPM240T100C5

  • CPLD MAX II Family 192 Macro Cells 1879.7MHz 0.18um Technolo...

  • 101頁

  • Altera   Altera

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1鈥?
Chapter 1: Introduction
Features
Table 1鈥?
shows the MAX II family features.
Table 1鈥?.
MAX II Family Features
Feature
LEs
Typical Equivalent Macrocells
Equivalent Macrocell Range
UFM Size (bits)
Maximum User I/O pins
t
PD1
(ns)
(1)
f
CNT
(MHz)
(2)
t
SU
(ns)
t
CO
(ns)
Notes to
Table 1鈥?:
(1) t
PD1
represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic
implemented in a single LUT and LAB that is adjacent to the output pin.
(2) The maximum frequency is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number.
EPM240
EPM240G
240
192
128 to 240
8,192
80
4.7
304
1.7
4.3
EPM570
EPM570G
570
440
240 to 570
8,192
160
5.4
304
1.2
4.5
EPM1270
EPM1270G
1,270
980
570 to 1,270
8,192
212
6.2
304
1.2
4.6
EPM2210
EPM2210G
2,210
1,700
1,270 to 2,210
8,192
272
7.0
304
1.2
4.6
EPM240Z
240
192
128 to 240
8,192
80
7.5
152
2.3
6.5
EPM570Z
570
440
240 to 570
8,192
160
9.0
152
2.2
6.7
f
For more information about equivalent macrocells, refer to the
MAX II Logic Element to
Macrocell Conversion Methodology
white paper.
MAX II and MAX IIG devices are available in three speed grades: 鈥?, 鈥?, and 鈥?, with
鈥? being the fastest. Similarly, MAX IIZ devices are available in two speed grades: 鈥?,
鈥?, with 鈥? being faster. These speed grades represent the overall relative
performance, not any specific timing parameter. For propagation delay timing
numbers within each speed grade and density, refer to the
DC and Switching
Characteristics
chapter in the
MAX II Device Handbook.
Table 1鈥?
shows MAX II device speed-grade offerings.
Table 1鈥?.
MAX II Speed Grades
Speed Grade
Device
EPM240
EPM240G
EPM570
EPM570G
EPM1270
EPM1270G
EPM2210
EPM2210G
EPM240Z
EPM570Z
鈥?/div>
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鈥?/div>
鈥?/div>
鈥?/div>
v
v
v
v
v
v
v
鈥?/div>
鈥?/div>
v
v
v
鈥?/div>
鈥?/div>
v
v
v
鈥?/div>
鈥?/div>
鈥?
v
鈥?
v
鈥?
v
鈥?
鈥?/div>
鈥?
鈥?/div>
MAX II Device Handbook
漏 October 2008 Altera Corporation

EPM240T100C5 產(chǎn)品屬性

  • 270

  • 集成電路 (IC)

  • 嵌入式 - CPLD（復(fù)雜可編程邏輯器件）

  • MAX® II

  • 系統(tǒng)內(nèi)可編程

  • 4.7ns

  • 2.5V，3.3V

  • 240

  • 192

  • -

  • 80

  • 0°C ~ 85°C

  • 表面貼裝

  • 100-TQFP

  • 100-TQFP（14x14）

  • 托盤

  • 544-1146

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