7 Application Notes
7.1
Design Tips
The following are recommendations for the design of circuits that utilize a PMD Motion Processor.
Serial Interface
If the serial configuration decode logic is not implemented (see section 7.2) the CP data bus should
be tied high. This places the serial interface in a default configuration of 9600,n,8,1 after power on
or reset.
Controlling pulse output during reset
When the motion processor is in a reset state (when the reset line is held low) or immediately after a
power on, the pulse outputs can be in an unknown state, causing undesirable motor movement. It is
recommended that the enable line of any motor amplifier be held in a disabled state by the host
processor or some logic circuitry until communication to the motion processor is established. This
can be in the form of a delay circuit on the amplifier enable line after power up, or the enable line can
be ANDed with the CP reset line.
Parallel word encoder input
When using parallel word input for motor position, it is useful to also decode this information into
the User I/O space. This allows the current input value to be read using the chip instruction ReadIO
for diagnostic purposes.
Using a non standard system clock frequency
It is often desirable to share a common clock among several components in a design. In the case of
the PMD Motion Processors it is possible to use a clock below the standard value of 20MHz. In this
case all system frequencies will be reduced as a fraction of the input clock verses the standard
20MHz clock. The list below shows the affected system parameters:-
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Serial baud rate
Maximum pulse rate
Timing characteristics as shown in section 3.2
Cycle time
For example, if an input clock of 17MHz is used with a serial baud rate of 9600 the following timing
changes will result:-
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Serial baud rate decreases to 9600 bps *17/20 = 8160 bps
Maximum step rate decreases to 50K pulses *17/20 = 42.5K pulses
Cycle time per axis increases to 102.4
碌sec
*20/17 = 120.48
碌sec
MC3510 Technical Specifications
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