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MC34701EK Datasheet

  • MC34701EK

  • Freescale Semiconductor, Inc [1.5 A Switch-Mode Power Suppl...

  • FREESCALE

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DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued)
Characteristics noted under conditions -40擄C
鈮?/div>
T
A
鈮?/div>
85擄C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3 V using
the typical application circuit (see
Figures 33)
unless otherwise noted.
Characteristic
Boost Regulator
Boost Regulator MOSFET Maximum ON Time
(20)
Boost Regulator Control Loop Propagation Delay
(20)
Boost Switching Node VBD Rise Time
(20)
IBST = 20 mA
Boost Switching Node VBD Fall Time
(20)
IBST = 20 mA
Linear Regulator (LDO)
Fault Condition Time-Out
Retry Timer Cycle
Reset Monitor (
RST
)
Monitoring LFB Terminal Delay
Monitoring INV Terminal Delay
SCA, SCL Terminal, I
2
C Bus (Standard)
SCL Clock Frequency
(20)
Bus Free Time Between a STOP and a START Condition
(20)
Hold Time (Repeated) START Condition (After this period, the first clock
pulse is generated.)
(20)
Symbol
Min
Typ
Max
Unit
t
ON
t
BST_PD
t
B_RISE
鈥?/div>
鈥?/div>
24
50
鈥?/div>
鈥?/div>
碌s
ns
ns
鈥?/div>
t
B_FALL
鈥?/div>
5.0
ns
3.0
鈥?/div>
t
FAULT
t
Ret
7.0
70
10
100
15
150
ms
ms
t
D_RST_LFB
t
D_RST_INV
12
12
鈥?/div>
鈥?/div>
28
28
碌s
碌s
f
SCL
t
BUF
t
HD-STA
t
LOW
t
HIGH
t
F
t
SU-STA
t
HD-DAT
t
SU-DA
T
t
SU-STO
C
B
鈥?/div>
4.7
鈥?/div>
鈥?/div>
100
鈥?/div>
kHz
碌s
碌s
4.0
4.7
4.0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
碌s
碌s
ns
Low Period of the SCL Clock
(20)
High Period of the SCL Clock
(20)
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10 pF to 400
pF, 3.0 mA Sink Current
(20), (22)
鈥?/div>
4.7
0.0
250
4.0
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
250
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
400
碌s
碌s
ns
碌s
pF
Setup Time for a Repeated START Condition
(20)
Data Hold Time for I
2
C Bus Devices
(20)
,
(21)
Data Setup Time
(20)
Setup Time for STOP Condition
(20)
Capacitive Load for Each Bus Line
(20)
Notes
20. Design information only. This parameter is not production tested.
21. The device provides an internal hold time of at least 300 ns for the SDA signal (refer to the V
IH_MIN
of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
22.
VIH is High Level Voltage on I
2
C bus lines and VIL is Low Level Voltage on I
2
C bus lines
34701
12
Analog Integrated Circuit Device Data
Freescale Semiconductor

MC34701EK 產(chǎn)品屬性

  • 42

  • 集成電路 (IC)

  • PMIC - 穩(wěn)壓器 - 專用型

  • -

  • 轉(zhuǎn)換器，F(xiàn)reescale 電源 QUICC? I，II

  • 2.8 V ~ 6 V

  • 1

  • 可調(diào)

  • -40°C ~ 85°C

  • 表面貼裝

  • 32-SOIC（0.295"，7.50mm 寬）

  • 32-SOIC

  • 管件

  • KIT33701DWBEVB-ND - KIT FOR 33701 POWER SUPPLY

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