鈥?/div>
+
+2.0 V
0
鈥?.0 V
R5
*Polycarbonate or
Polystyrene Capacitor
VEE
Overshoot 10%
ts = 10
碌s
When driving large CL, the VO slew rate is determined by CL
and IO(max):
t
Time (t) = R4 Cn (VR/VR鈥揤I), R3 = R4, R5 = 0.1 R6
If R1 = R2: t = 0.693 R4C
Design Example: 100 Second Timer
VR = 10 V C = l.0
碌F
R3 = R4 = 144 M
R6 = 20 k R5 = 2.0 k R1 = R2 = 1.0 k
鈭哣
O IO
0.02
=
=
V/碌s = 0.04 V/碌s (with CL shown)
0.5
鈭唗
CL
Figure 16. Wide BW, Low Noise,
Low Drift Amplifier
C2
R2
7
2
3
4
Sr
Power BW: fmax =
2蟺 Vp
VCC
8
6
fmax
^
240 kHz
R1
Vin
C1
10 V
鈥?0 V
MC34001
^
240 kHz
Parasitic input capacitance (C1
^
3.0 pF plus any additional layout capacitance)
interacts with feedback elements and creates undesirable high鈥揻requency pole.
To compensate add C2 such that: R2C2
^
R1C1.
VEE
MOTOROLA ANALOG IC DEVICE DATA
7