鈩?/div>
with V+ from 5 V to 30 V; and over the full input common-mode range (0 V to V+ 鈥?.5 V).
2. The direction of the input current is out of the IC due to the PNP input stage. This current is essentially constant, independent of the state of
the output so no loading change exists on the input lines.
3. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of
the common-mode voltage range is V+ 鈥?.5 V, but either or both inputs can go to +32 V without damage.
4. Due to proximity of external components, insure that coupling is not originating via stray capacitance between these external parts. This
typically can be detected as this type of capacitance coupling increases at higher frequencies.
5. Short-circuits from the output to V+ can cause excessive heating and eventual destruction. The maximum output current is approximately
40 mA independent of the magnitude of V+. At values of supply voltage in excess of +15 V
DC
, continuous short-circuits can exceed the
power dissipation ratings and cause eventual destruction.
6. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3 V. The upper end of
the common-mode voltage range is V+ 鈥?.5 V, but either or both inputs can go to +32 V
DC
without damage.
2002 Jul 12
5