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LT1533C Datasheet

  • LT1533C

  • Linear Technology [Ultralow Noise 1A Switching Regulator]

  • LINER

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LT1533
BLOCK DIAGRA
V
C
LDO REGULATOR
+
鈥?/div>
100k
NFB
NEGATIVE
FEEDBACK
AMP
50k
INTERNAL V
CC
FB
+
1.25V
R
T
OSCILLATOR
C
T
SYNC
T
FF
BK
GND
DUTY
1533 BD
OPERATIO
In noise sensitive applications, switching regulators tend
to be ruled out as a power supply option due to their
propensity for generating unwanted noise. When switch-
ing supplies are required due to efficiency or input/output
voltage constraints, great pains must be taken to work
around the noise generated by a typical supply. These
steps may include precise synchronization of the power
supply oscillator to an external clock, synchronizing the
rest of the circuit to the power supply oscillator, or halting
power supply switching during noise sensitive operations.
The LT1533 greatly simplifies the task of eliminating
supply noise by enabling the design of an inherently low
noise switching regulator power supply.
The LT1533 is a fixed frequency, current mode switching
regulator with unique circuitry to control the voltage and
current slew rates of the output switches. Slew control
capability provides much greater control over power sup-
6
+
g
m
ERROR
AMP
鈥?/div>
+
鈥?/div>
W
SHDN
V
IN
PGND COL A
COL B
+
鈥?/div>
OUTPUT
DRIVERS
R
VSL
SLEW CONTROL
COMP
R
CSL
S
FF
R
Q
Q
QB
U
ply components that can create conducted and radiated
electromagnetic interference. The current mode control
provides excellent AC and DC line regulation and simplifies
loop compensation.
Current Mode Control
A switching cycle begins with an oscillator discharge pulse
which resets the RS flip-flop, turning on one of the output
drivers (refer to Block Diagram). The switch current is
sensed across an internal resistor and the resulting volt-
age is amplified and compared to the output of the error
amplifier (V
C
pin). The driver is turned off once the output
of the current sense amplifier exceeds the voltage on the
V
C
pin. The toggle flip-flop ensures that the two output
drivers are enabled on alternate clock cycles. Internal
slope compensation is provided to ensure stability under
high duty cycle conditions.

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