LT1512
OPERATION
current amplifier is set to a fixed gain of 鈥?12.5 which
provides a 鈥?100mV current limit sense voltage.
The error signal developed at the amplifier output is
brought out externally and is used for frequency compen-
sation. During normal regulator operation this pin sits at a
voltage between 1V (low output current) and 1.9V (high
output current). Switch duty cycle goes to zero if the V
C
pin
is pulled below the V
C
pin threshold, placing the LT1512 in
an idle mode.
APPLICATIONS INFORMATION
The LT1512 is an IC battery charger chip specifically opti-
mized to use the SEPIC converter topology. The SEPIC
topology has unique advantages for battery charging. It will
operate with input voltages above, equal to or below the
battery voltage, has no path for battery discharge when
turned off and eliminates the snubber losses of flyback
designs. It also has a current sense point that is ground
referred and need not be connected directly to the battery.
The two inductors shown are actually just two identical
windings on one inductor core, although two separate
inductors can be used.
A current sense voltage is generated with respect to ground
across R3 in Figure 1. The average current through R3 is
always identical to the current delivered to the battery. The
LT1512 current limit loop will servo the voltage across R3 to
鈥?100mV when the battery voltage is below the voltage limit
set by the output divider R1/R2. Constant current charging
is therefore set at 100mV/R3. R4 and C4 filter the current
signal to deliver a smooth feedback voltage to the I
FB
pin. R1
and R2 form a divider for battery voltage sensing and set the
battery float voltage. The suggested value for R2 is 12.4k. R1
is calculated from:
tional uncorrectable error to the constant voltage float mode
of about
鹵0.5%
as calculated by:
V
BAT
Error =
鹵
0.15
碌
A(R1)(R2)
1.245(R1+ R2)
R1
=
R2(V
BAT
鈥?1.245)
1.245
+
R2(0.3
碌
A)
V
BAT
= battery float voltage
0.3碌A(chǔ) = typical FB pin bias current
A value of 12.4k for R2 sets divider current at 100碌A(chǔ). This is
a constant drain on the battery when power to the charger is
off. If this drain is too high, R2 can be increased to 41.2k,
reducing divider current to 30碌A(chǔ). This introduces an addi-
6
U
W
U
U
U
鹵0.15碌A(chǔ)
= expected variation in FB bias current around
the nominal 0.3碌A(chǔ) typical value.
With R2 = 41.2k and R1 = 228k, (V
BAT
= 8.2V), the error due
to variations in bias current would be
鹵0.42%.
A second option is to disconnect the voltage divider with a
small NMOS transistor as shown in Figure 3. To ensure
adequate drive to the transistor (even when the V
IN
voltage is
at its lowest operating point of 2.4V), the FET gate is driven
wth a peak detected voltage via D2. Note that there are two
connections for D2. The L1 A connection must be used if the
voltage divider is set for less than 3.5V (fully charged
battery). Gate drive is equal to battery voltage
plus
input
voltage. The disadvantage of this connection is that Q1 will
still be 鈥渙n鈥?if the V
IN
voltage is active and the charger is shut
down via the S/S pin. The L1 B connection allows Q1 to turn
off when V
IN
is off or when shutdown is initiated, but the
reduced gate drive (=V
BAT
) is not adequate to ensure a Q1
on-state for fully charged battery voltages less than 3.5V. Do
not substitute for Q1 unless the new device has adequate
V
GS
maximum rating, especially if D2 is connected to L1A.
C6 filters the gate drive and R5 pulls the gate low when
switching stops.
Disconnecting the divider leaves only D1 diode leakage as a
battery drain. See Diode Selection for a discussion of diode
leakage.
1
2
3
4
5
6
7
8
9
10
11
12
