LT1512
PIN FUNCTIONS
be connected directly to the GND S pin or to the ground
plane close to the point where the GND S pin is connected.
V
SW
:
The switch pin is the collector of the power switch,
carrying up to 1.5A of current with fast rise and fall times.
Keep the traces on this pin as short as possible to minimize
radiation and voltage spikes. In particular, the path in
Figure 1 which includes SW to C2, D1, C1 and around to
the LT1512 ground pin should be as short as possible to
minimize voltage spikes at switch turn-off.
BLOCK DIAGRAM
S/S
5k
I
FB
62k
FB
1.245V
REF
GND S
OPERATION
The LT1512 is a current mode switcher. This means that
switch duty cycle is directly controlled by switch current
rather than by output voltage or current. Referring to the
Block Diagram, the switch is turned 鈥渙n鈥?at the start of each
oscillator cycle. It is turned 鈥渙ff鈥?when switch current
reaches a predetermined level. Control of output voltage
and current is obtained by using the output of a dual
feedback voltage sensing error amplifier to set switch
current trip level. This technique has the advantage of
simplified loop frequency compensation. A low dropout
internal regulator provides a 2.3V supply for all internal
circuitry on the LT1512. This low dropout design allows
input voltage to vary from 2.7V to 25V. A 500kHz oscillator
is the basic clock for all internal timing. It turns 鈥渙n鈥?the
output switch via the logic and driver circuitry. Special
adaptive antisat circuitry detects onset of saturation in the
power switch and adjusts driver current instantaneously to
limit switch saturation. This minimizes driver dissipation
and provides very rapid turn-off of the switch.
A unique error amplifier design has two inverting inputs
which allow for sensing both output voltage and current. A
1.245V bandgap reference biases the noninverting input.
The first inverting input of the error amplifier is brought out
for positive output voltage sensing. The second inverting
input is driven by a 鈥渃urrent鈥?amplifier which is sensing
output current via an external current sense resistor. The
+
鈥?/div>
鈥?/div>
W
U
U
U
U
V
IN
SHUTDOWN
DELAY AND RESET
500kHz
OSC
LOW DROPOUT
2.3V REG
SW
ANTI-SAT
SYNC
LOGIC
DRIVER
SWITCH
+
I
FBA
鈥?/div>
COMP
+
EA
V
C
A
V
鈮?/div>
6
IA
0.08鈩?/div>
鈥?/div>
GND
1512 F02
Figure 2
5
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