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LT1510I Datasheet

  • LT1510I

  • Linear Technology [Constant-Voltage/ Constant-Current Batte...

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LT1510/LT1510-5
APPLICATIONS INFORMATION
Example: V
IN
= 15V, V
BAT
= 8.4V, I
BAT
= 1.2A;
P
BIAS
=
3
.
5mA 15
+
1
.
5mA 8
.
4
+
(
8
.
4
)
15
(
)( )
( )
2
[
7
.
5mA
+
(
0
.
012
)(
1
.
2
)
]
=
0
.
17W
2
錚?/div>
8
.
4
錚?/div>
1
.
2 8
.
4
錚?/div>
1
+
30
錚?/div>
錚?/div>
錚?/div>
P
DRIVER
P
SW
( )( )
=
55
(
15
)
2
1.2
) (
0.35
)(
8.4
)
(
=
+
15
=
0
.
13W
錚?/div>
10 鈥?10
鈭?/div>
9
錚?/div>
15 1. 2 200kHz
錚?/div>
錚?/div>
=
0.28
+
0.04
=
0.32W
P
SENSE
=
0.18 1.2
( )( )(
2
)
( )( )
=
0.26W
Total power in the IC is:
0.17 + 0.13 + 0.32+ 0.26 = 0.88W
Temperature rise will be (0.88W)(50擄C/W) = 44擄C. This
assumes that the LT1510 is properly heat sunk by con-
necting the four fused ground pins to the expanded traces
and that the PC board has a backside or internal plane for
heat spreading.
The P
DRIVER
term can be reduced by connecting the boost
diode D2 (see Figures 2 and 6 circuits) to a lower system
voltage (lower than V
BAT
) instead of V
BAT
(see Figure 8).
THERMAL RESISTANCE (擄C/W)
L1
D2
SENSE
V
X
I
VX
SW
C1
LT1510
BOOST
Then,
P
DRIVER
(
I
)(
V
)( )
=
55
(
V
)
BAT
BAT
IN
錚?/div>
V
錚?/div>
V
X
錚?/div>
1
+
X
錚?/div>
錚?/div>
30
錚?/div>
For example, V
X
= 3.3V,
P
DRIVER
( )( )( )
=
55
(
15V
)
錚?/div>
3
.
3V
錚?/div>
1
.
2A 8
.
4V 3
.
3V
錚?/div>
1
+
30
錚?/div>
錚?/div>
錚?/div>
=
0
.
045W
U
W
U
U
The average I
VX
required is:
P
DRIVER
0
.
045W
=
=
14mA
V
X
3
.
3V
Total board area becomes an important factor when the
area of the board drops below about 20 square inches. The
graph in Figure 9 shows thermal resistance vs board area
for 2-layer and 4-layer boards. Note that 4-layer boards
have significantly lower thermal resistance, but both types
show a rapid increase for reduced board areas. Figure 10
shows actual measured lead temperature for chargers
operating at full current. Battery voltage and input voltage
will affect device power dissipation, so the data sheet
power calculations must be used to extrapolate these
readings to other situations.
Vias should be used to connect board layers together.
Planes under the charger area can be cut away from the
rest of the board and connected with vias to form both a
+
10碌F
1510 F07
Figure 8
60
55
50
45
40
35
30
25
0
5
20
15
25
10
2
BOARD AREA (IN )
30
35
S16, MEASURED FROM AIR AMBIENT
TO DIE USING COPPER LANDS AS
SHOWN ON DATA SHEET
4-LAYER BOARD
2-LAYER BOARD
1510 F08
Figure 9. LT1510 Thermal Resistance
13

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