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LT1508I Datasheet

  • LT1508I

  • Linear Technology [Power Factor and PWM Controller(Voltage ...

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LT1508
PIN FUNCTIONS
R
SET
(Pin 15):
A resistor from R
SET
to GND sets the
oscillator charging current and the maximum multiplier
output current which is used to limit the maximum line
current.
I
M(MAX)
= 3.75V/R
SET
SS1 (Pin 16):
Soft Start. SS1 is reset to zero for low V
CC
.
When V
CC
rises above the lockout threshold, SS1 is
released to ramp up at a rate set by the internal 12碌A(chǔ)
current source and an external capacitor. During this ramp
up, PFC reference voltage is equal to SS1 voltage. After
SS1 rises past 7.5V, reference voltage remains at 7.5V.
V
CC
(Pin 17):
This is the supply for the chip. The LT1508
has two fast gate drivers required to fast charge high
power MOSFET gate capacitances. Good supply bypass-
ing is required consisting of a 0.1碌F ceramic capacitor in
parallel with a low ESR electrolytic capacitor (56碌F or
higher) in close proximity to IC GND.
APPLICATIONS INFORMATION
Voltage Error Amplifier (PFC Section)
The voltage error amplifier has a 100dB DC gain and 3MHz
unity-gain frequency. The output is internally clamped at
13.3V with V
CC
= 18V. Maximum error amp output voltage
decreases to V
CC
鈥?1.5V for V
CC
less than 12V. The
noninverting input is tied to the 7.5V
REF
through a diode
and can be pulled down with the SS1 pin. Referring to
Figure 1, V
OUT
= V
REF
[(R1 + R2)/R2]. With R1 = 1M and
R2 = 20k, V
OUT
= 382V. R1 through R4, C1 and C2 form the
compensation for the voltage loop. Gain of the voltage
error amp with the values shown is given by:
VA
OUT
= 鈥?/div>
V
OUT
1+j
C2
0.047碌F
C1
0.47碌F
(j)(f)(6.6) 1 + j f
11
) )
(R
REF
)(P
IN
)
R
S
(R
IAC
+ 25k)
f
1
The small-signal gain for the remaining portion of the
voltage loop for frequencies below the current loop band-
width is (see Figure 2):
V
OUT
V
IN
=
VA
OUT
(5蟺)(j)(f)(C
OUT
)(V
OUT
)
U
W
U
U
U
U
U
(For application help with the PFC portion of this chip, see the LT1248 data sheet)
PWM SECTION
SS2 (Pin 13):
PWM Soft Start. The comparator PWMOK
monitors the OVP pin and releases the SS2 after the PFC
output gets close to the final voltage.
V
C
(Pin 18):
PWM voltage mode control voltage. Normally
connects to the optocoupler amplifier output. A pull-up
current of 50碌A(chǔ) flows out of the pin.
I
LIM
(Pin 19):
PWM current sense input with limit set to
1.1V.
GTDR2 (Pin 20):
The PWM MOSFET gate driver is a 1.5A
fast totem pole output. It is clamped at 15V. Capacitive
loads like the MOSFET gates may cause overshoot. A gate
series resistor of at least 5鈩?will prevent the overshoot.
REGULATOR OUTPUT
V
OUT
= 382V
R3
20k
V
SENSE
R4
330k
R1
1M
鈥?/div>
+
7.5V
REF
ERROR AMP
VA
OUT
R2
20k
OVP
LT1508
鈥?/div>
+
1.05V
REF
OVERVOLTAGE
COMPARATOR
1508 鈥?F01
Figure 1
With V
IN
= 120VAC, P
IN
= 150W, R
S
= 0.15鈩? R
REF
= 4k,
R
IAC
= 1M, V
OUT
= 382V and C
OUT
= 470碌F, V
OUT
/VA
OUT
=
85/(j)(f). At very low frequencies, the loop has a 鈥?40dB/
decade slope. Additional zero-pole compensation is added
at 1Hz and 11Hz. The resulting loop gain and phase margin
is shown in Figure 3. The unity-gain bandwidth is low
compared to 120Hz, which results in low distortion and a
high power factor.
7

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