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LT1508I Datasheet

  • LT1508I

  • Linear Technology [Power Factor and PWM Controller(Voltage ...

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LT1508
APPLICATIONS INFORMATION
input up to V
C
and then the SS2 voltage continues beyond
V
C
. The PWMOK comparator contains hysteresis and will
pull SS2 low disabling the PWM section if the PFC output
voltage falls below approximately 62% of its preset value
(240V with nominal 382V output).
Start-Up and Supply Voltage
The LT1508 draws only 250碌A(chǔ) before the chip starts at
16V on V
CC
. To trickle start, a 91k resistor from the power
line to V
CC
supplies trickle current, and C4 holds V
CC
up
while switching starts (see Figure 8); then the auxiliary
winding takes over and supplies the operating current.
Note that D3 and the larger values of C3 are only necessary
for systems that have sudden large load variations down
to minimum load and/or very light load conditions. Under
these conditions the loop may exhibit a start/restart mode
because switching remains off long enough for C4 to
discharge below 10V. Large values for C3 will hold V
CC
up
until switching resumes. For less severe load variations D3
is replaced with a short and C3 is omitted. The turns ratio
between the primary winding determines V
CC
according to :
Output Capacitor (PFC Section)
GTDR2 (PWM) pulse is synchronized to GTDR1 (PFC) pulse
with 53% duty cycle delay to reduce RMS ripple current in the
output capacitor. See PFC/PWM Synchronization graph in
the Typical Performance Characteristics section.
The peak-to-peak 120Hz PFC output ripple is determined by:
V
OUT
N
=
P
V
CC
鈥?2V N
S
for 382V V
OUT
and 18V V
CC
, Np/Ns
鈮?/div>
19.
LINE
MAIN INDUCTOR
N
P
N
S
D1
R1
91k
1W
D3
+
D2
C1
2碌F
C2
2碌F
+
+
C3
390碌F
+
Figure 8
U
W
U
U
V
P-P
= 2I
LOAD(DC)
(Z)
where I
LOAD(DC)
is the DC load current of the PWM stage
and Z is the capacitor impedance at 120Hz.
For 470碌F, impedance is 2.8鈩?at 120Hz. At 335W load,
I
LOAD(DC)
= 335V/382V = 0.88A, V
P-P
= (2)(0.88)(2.8鈩? =
5V. If less ripple is desired higher capacitance should be
used. The selection of the output capacitor is based on
voltage ripple, hold-up time and ripple current. Assuming
the DC converter (PWM section) is designed to operate
with 240V to 382V
IN
, the minimum hold-up time is a
function of the energy storage capacity of the capacitor:
t
HOLD
=
(0.5)C
OUT
(382V 鈥?0.5V
P鈥揚(yáng)
)
2
鈥?240V
2
P
OUT
with C
OUT
= 470碌F, V
P-P
= 11.5V, and P
OUT
= 335W,
t
HOLD
= 60ms which is 3.6 line cycles at 60Hz. The ripple
current can be divided into two major components. The
first is the 120Hz component which is related to the DC
load current as follows:
I
120HZ
鈮?/div>
I
LOAD(DC)
鈭?/div>
2
The second component is made up of switching frequency
components due to the PFC stage charging the capacitor
and the PWM stage discharging the capacitor. For a 300W
output PFC forward converter running from an input
voltage of 100V
RMS
, the total high frequency ripple current
was measured to be 1.79A
RMS
.
For the United Chemicon KMH 450V capacitor series,
ripple current at 100kHz is specified 1.43 times higher
than the 120Hz limit.
V
CC
C4
100碌F
1508 鈥?F08
11

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