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LT1508I Datasheet

  • LT1508I

  • Linear Technology [Power Factor and PWM Controller(Voltage ...

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LT1508
APPLICATIONS INFORMATION
line current reaches the secondary limit, the comparator
takes over control and hysteresis may occur causing
audible noise.
Overvoltage Protection (PFC Section)
Because of the slow loop response necessary for power
factor correction, output overshoot can occur following a
sudden load reduction or removal. To protect downstream
components, the LT1508 provides an overvoltage com-
parator which senses the output voltage and quickly
reduces the line current demand. Referring back to Figure
1, V
OUT
is 382V and during normal operation, since no
current flows in R3, 7.5V appears at both the V
SENSE
and
OVP pins. When V
OUT
overshoots its preset value, the
overcurrent from R1 will flow through R2 as well as R3.
The voltage amplifier feedback will keep V
SENSE
at 7.5V.
Therefore, the equivalent AC resistance seen by the OVP
pin is R2 in parallel with R3 or 10k. With these values and
the overvoltage comparator trip level internally set at
1.05V
REF
, the comparator trips when V
OUT
overshoots
10%. Overvoltage trip level is given by:
R4
1.05M
0.047碌F
0.47碌F
V
OUT
R1
1M
R2
20k
330k
1.05V
REF
V
OUT
= 382V
OVERVOLTAGE = 420V
1508 鈥?F07
Figure 7
(%)V
OUT
= 5%
(
R2 + R3
R3
)
this condition, the amplifier M1 (see Block Diagram)
becomes active. When VA
OUT
reduces to 2.2V, M1 sup-
plies up to 7碌A(chǔ) of current to the resistor at the I
SENSE
pin
in order to cancel a negative V
OS
and keep V
OUT
error to
within 2V.
Undervoltage Lockouts and Soft Start
The LT1508 turns on when V
CC
reaches 16V and remains
on until V
CC
falls below 10V, whereupon the chip enters the
lockout state. In the lockout state, the oscillator is off and
the V
REF
and gate driver pins remain low. A capacitor from
SS1 to GND1 determines the ramp-up time of the PFC
section. SS1 is released from a zero when V
CC
rises above
the lockout threshold. Once released, an internal 14碌A(chǔ)
current source ramps the voltage error amplifier鈥檚 refer-
ence voltage to 7.5V. SS1 voltage then continues beyond
7.5V. A second capacitor from SS2 to GND1 determines
the start-up time from the PWM section. A PWMOK
comparator (see Block Diagram) holds SS2 low until the
OVP pin reaches 7V. This corresponds to the PFC output
voltage reaching approximately 93% of its preset voltage.
SS2 is diode coupled to the PMW comparator which is
connected to the V
C
pin by a second diode. Holding SS2
low at any time will disable PWM output. Once released,
the 14碌A(chǔ) current source ramps the PWM comparator
For additional protection, the OVP pin can be connected
to V
OUT
through an independent resistor divider (see
Figure 7). This ensures overvoltage protection during
safety agency abnormal testing conditions, such as
opening R1 or shorting R2.
The output of the multiplier looks like a high impedance
current source. In the current loop, offset line current is
determined by multiplier offset current and input offset
voltage of the current error amplifier. A 鈥?4mV current
amplifier V
OS
translates to 27mA line current and 6.7W
input power for 250VAC line if a 0.15鈩?sense resistor is
used. Under a no-load condition or when the load power
is less than the offset output power, the offset line current
could slowly charge the output to an overvoltage level.
This is because the best the overvoltage comparator can
do is to reduce the multiplier output current to zero.
Unfortunately, this does not guarantee zero output current
if the current amplifier has offset. To regulate V
OUT
under
10
+
R5
20k
鈥?/div>
OVP
+
鈥?/div>
U
W
U
U
V
SENSE
VA
OUT
ERROR
AMP
LT1508
OVERVOLTAGE
COMPARATOR

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