0&3
* Input Stage Common-Mode Clamping
*
ECM
55 4 3 64 1
RCM
DCMP
VCMP
RST
DST
VST
57 56
56 55
57 4
58 59
59 55
58 4
1K
DY
1.2
1K
DX
1.6
GCMP2 23 4 POLY(2) 57 56 58 59
0 0 0;0 -500U 500U
*
* Input Errors (vos, en, psr)
*
ERR
64 1 poly(2) 67 4 3 4
-50U 2.3 6U
*
* Second Stage, pole at 0.19Hz
*
GS
23 4 8 9 181U
R1
23 4 5.53G
C2
23 4 166P
VSOM
VSOP
DSOM
DSOP
*HCM
3 24
25 4
23 24
25 23
23
3
4.784
-3.98
DY
DY
VCMP
FS
3 4 POLY(11) VO3 VO5 VO4 VO6 VO1 VO2 VO9 VO10 VMID1 VSOP VSOM
+ 200U -1 -1 -1 1 -1 -1 1 1 -1 -1 -1
*
* Mid-supply Reference
*
RMID1
3 35 61.62K
VMID1 35 34 0
RMID2
4 34 61.62K
ELEVEL 34 4 23 4 -1
*
* Output Stage
*
DO3
34 43 DY
DO4
44 34 DY
DO5
3 45 DY
DO6
3 46 DY
DO7
4 45 DY
DO8
4 46 DY
VO3
43 5 0.1
VO4
5 44 30M
GO5
VO5
GO6
VO6
GO1
VO1
GO2
VO2
RO9
VO9
RO10
VO10
3 47 3 34
47 5 0
4 48 34 4
48 5 0
49 4 5 34
49 45 0
50 4 34 5
50 46 0
3 51 100
51 5 0
52 4 100
52 5 0
10M
10M
10M
10M
'6$SDJH
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