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AD7934-6 Datasheet

  • AD7934-6

  • 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer

  • 30頁(yè)

  • AD

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AD7934-6
POWER VS. THROUGHPUT RATE
A considerable advantage of powering the ADC down after a
conversion is that the part鈥檚 power consumption is significantly
reduced at lower throughput rates. When using the different
power modes, the AD7934-6 is only powered up for the
duration of the conversion. Therefore, the average power
consumption per cycle is significantly reduced. Figure 39 shows
a plot of the power vs. the throughput rate when operating in
autostandby mode for both V
DD
= 5 V and 3 V.
For example, if the device runs at a throughput rate of 10 kSPS,
then the overall cycle time would be 100 碌s. If the maximum
CLKIN frequency of 10 MHz is used, the conversion time
accounts for only 1.315 碌s of the overall cycle time while the
AD7938-6 stays in standby mode for the remainder of the cycle.
If an external reference is used, the power-up time reduces to
600 ns; therefore, the AD7934-6 remains in standby for a
greater time in every cycle. Additionally, the current
consumption when converting should be lower than the
specified maximum of 1.5 mA or 1.2 mA with V
DD
= 5 V or 3 V,
respectively.
Figure 40 shows a plot of the power vs. the throughput rate
when operating in normal mode for both V
DD
= 5 V and 3 V.
Again, when using an external reference, the current
consumption when converting is lower than the specified
maximum. In both plots, the figures apply when using the
internal reference.
2.0
1.8
1.6
1.4
POWER (mW)
7
T
A
= 25
擄
C
6
V
DD
= 5V
5
POWER (mW)
4
3
V
DD
= 3V
2
0
0
100
200
300
400
500
THROUGHPUT (kSPS)
600
700
Figure 40. Power vs. Throughput in Normal Mode Using Internal Reference
MICROPROCESSOR INTERFACING
AD7934-6 to ADSP-21xx Interface
Figure 41 shows the AD7934-6 interfaced to the ADSP-21xx
series of DSPs as a memory-mapped device. A single wait state
could be necessary to interface the AD7934-6 to the ADSP-
21xx, depending on the clock speed of the DSP. The wait state
can be programmed via the data memory wait state control
register of the ADSP-21xx (see the ADSP-21xx family User鈥檚
Manual for details). The following instruction reads from the
AD7934-6:
MR
=
DM
(ADC)
where:
ADC
is the address of the AD7934-6.
DSP/USER SYSTEM
T
A
= 25
擄
C
V
DD
= 5V
A0 TO A15
ADDRESS BUS
1.2
1.0
0.8
V
DD
= 3V
0.6
0.4
0.2
0
0
20
40
60
80
THROUGHPUT (kSPS)
100
04752-029
CONVST
ADSP-21xx
1
DMS
IRQ2
WR
RD
ADDRESS
DECODER
AD7934-6
1
CS
BUSY
WR
RD
DB0 TO DB11
04752-044
120
D0 TO D23
1
ADDITIONAL
DATA BUS
Figure 39. Power vs. Throughput in Autostandby Mode
Using Internal Reference
PINS OMITTED FOR CLARITY.
Figure 41. Interfacing to the ADSP-21xx
Rev. A | Page 25 of 28
04752-030
1

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