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AD7934-6 Datasheet

  • AD7934-6

  • 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer

  • 30頁

  • AD

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AD7934-6
The ADC then returns to Channel 0 and starts the sequence
again. The WR input must be kept high to ensure that the control
register is not accidentally overwritten and the sequence inter-
rupted. This pattern continues until the AD7934-6 is written to.
Figure 31 shows the flowchart of the consecutive sequence mode.
POWER ON
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT,
AND OUTPUT CONFIGURATION. SELECT
FINAL CHANNEL (ADD1 AND ADD0) IN
CONSECUTIVE SEQUENCE.
SET SEQ0 = SEQ1 = 1.
In all cases, the specified reference is 2.5 V.
The performance of the part with different reference values is
shown in Figure 9 , Figure 10, and Figure 11. The value of the
reference sets the analog input span and the common-mode
voltage range. Errors in the reference source result in gain
errors in the AD7934-6 transfer function and add to the
specified full-scale errors on the part.
Table 11 lists suitable voltage references available from Analog
Devices that can be used. Figure 33 shows a typical connection
diagram for an external reference.
Table 11. Examples of Suitable Voltage References
Reference
AD780
ADR421
ADR420
Output
Voltage
2.5/3
2.5
2.048
Initial Accuracy
(% max)
0.04
0.04
0.05
Operating
Current (碌A(chǔ))
1000
500
500
Figure 31. Consecutive Sequence Mode Flow Chart
REFERENCE SECTION
The AD7934-6 can operate with either the on-chip reference or
external reference. The internal reference is selected by setting
the REF bit in the internal control register to 1. A block diagram
of the internal reference circuitry is shown in Figure 32. The
internal reference circuitry includes an on-chip 2.5 V band gap
reference and a reference buffer. When using the internal refer-
ence, the V
REFIN
/V
REFOUT
pin should be decoupled to AGND with
a 0.47 碌F capacitor. This internal reference not only provides
the reference for the analog-to-digital conversion, but it can also
be used externally in the system. It is recommended that the
reference output is buffered using an external precision op amp
before applying it anywhere in the system.
BUFFER
V
REFIN
/
V
REFOUT
REFERENCE
04752-039
CONTINUOUSLY CONVERT ON A CONSECUTIVE
SEQUENCE OF CHANNELS FROM CHANNEL 0
UP TO AND INCLUDING THE PREVIOUSLY
SELECTED FINAL CHANNEL ON ADD1 AND ADD0
WITH EACH CONVST PULSE.
AD780
NC
V
DD
0.1碌F
10nF
0.1碌F
1
AD7934-6*
NC
NC
2.5V
NC
0.1碌F
V
REF
O/PSELECT
8
7
6
2
+V
IN
3
TEMP V
OUT
4
GND
TRIM
5
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
04752-041
Figure 33. Typical V
REF
Connection Diagram
Digital Inputs
The digital inputs applied to the AD7934-6 are not limited by
the maximum ratings that limit the analog inputs. Instead, the
digital inputs applied can go to 7 V. They are not restricted by
the AV
DD
+ 0.3 V limit that is on the analog inputs.
ADC
AD7934-6
04752-040
Figure 32. Internal Reference Circuit Block Diagram
Alternatively, an external reference can be applied to the
V
REFIN
/V
REFOUT
pin of the AD7934-6. An external reference
input is selected by setting the REF bit in the internal control
register to 0. The external reference input range is 0.1 V to V
DD
.
It is important to ensure that when choosing the reference value,
the maximum analog input range (V
IN MAX
) is never greater than
V
DD
+ 0.3 V, in order to comply with the maximum ratings of the
device. For example, if operating in differential mode and the
reference is sourced from V
DD
, then the 0 to 2 脳 V
REF
range cannot
be used. This is because the analog input signal range would now
extend to 2 脳 V
DD
, which would exceed maximum rating condi-
tions. In the pseudo differential modes, the user must ensure that
(V
REF
+ V
IN鈭?/div>
) 鈮?V
DD
when using the 0 to V
REF
range, or that (2 脳
V
REF
+ V
IN鈭?/div>
) 鈮?V
DD
when using the 2 脳 V
REF
range.
Another advantage of the digital inputs not being restricted by
the AV
DD
+ 0.3 V limit is that the power supply sequencing issues
are avoided. If any of these inputs are applied before AV
DD
, then
there is no risk of latch-up as there is on the analog inputs if a
signal greater than 0.3 V is applied prior to AV
DD
.
V
DRIVE
Input
The AD7934-6 also has a V
DRIVE
feature. V
DRIVE
controls the
voltage at which the parallel interface operates. V
DRIVE
allows the
ADC to easily interface to 3 V and 5 V processors. For example,
if the AD7934-6 is operated with an AV
DD
of 5 V, and the V
DRIVE
pin is powered from a 3 V supply, the AD7934-6 has better
dynamic performance with an AV
DD
of 5 V while still being able
to interface to 3 V processors. Care should be taken to ensure
V
DRIVE
does not exceed AV
DD
by more than 0.3 V (see the
Absolute Maximum Ratings section).
Rev. A | Page 20 of 28

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