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AD7934-6 Datasheet

  • AD7934-6

  • 4-Channel, 625 kSPS, 12-Bit Parallel ADC with a Sequencer

  • 30頁

  • AD

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AD7934-6
220鈩?/div>
2
脳
V
REF
p-p
440鈩?/div>
GND
V
REF
p-p
V+
27鈩?/div>
V
IN+
3.75V
2.5V
1.25V
V
IN+
AD7934-6*
V
IN鈥?/div>
V
REF
DC INPUT
VOLTAGE
0.47碌F
04752-037
04752-038
V鈥?/div>
220鈩?/div>
220鈩?/div>
220鈩?/div>
AD7934-6
3.75V
2.5V
1.25V
V
IN鈥?/div>
V
REF
V+
27鈩?/div>
A
V鈥?/div>
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 29. Pseudo Differential Mode Connection Diagram
20k鈩?/div>
04752-035
10k鈩?/div>
0.47
碌
F
ANALOG INPUT SELECTION
As shown in Table 9, users can set up their analog input con-
figuration by setting the values in the MODE0 and MODE1 bits
in the control register. Assuming the configuration has been
chosen, there are two different ways of selecting the analog
input to be converted, depending on the state of the SEQ0 and
SEQ1 bits in the control register.
Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
220鈩?/div>
V
REF
p-p
V
REF
GND
440鈩?/div>
V+
27鈩?/div>
3.75V
2.5V
1.25V
V
IN+
Traditional Multichannel Operation (SEQ0 = SEQ1 = 0)
AD7934-6
V鈥?/div>
220鈩?/div>
220鈩?/div>
V+
27鈩?/div>
A
V鈥?/div>
3.75V
2.5V
1.25V
V
IN鈥?/div>
V
REF
Figure 28. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
04752-036
10k鈩?/div>
0.47
碌
F
Any one of four analog input channels or two pairs of channels
can be selected for conversion in any order by setting the SEQ0
and SEQ1 bits in the control register to 0. The channel to be
converted is selected by writing to the address bits, ADD1 and
ADD0, in the control register to program the multiplexer prior to
the conversion. This mode of operation is that of a traditional
multichannel ADC, where each data write selects the next
channel for conversion. Figure 30 shows a flow chart of this mode
of operation. The channel configurations are shown in Table 9.
POWER ON
Another method of driving the AD7934-6 is to use the AD8138
differential amplifier. The AD8138 can be used as a single-
ended-to-differential amplifier or as a differential-to-differential
amplifier. The device is as easy to use as an op amp and greatly
simplifies differential signal amplification and driving.
WRITE TO THE CONTROL REGISTER TO
SET UP OPERATING MODE, ANALOG INPUT,
AND OUTPUT CONFIGURATION.
SET SEQ0 = SEQ1 = 0. SELECT THE DESIRED
CHANNEL TO CONVERT ON (ADD1 TO ADD0).
Pseudo Differential Mode
The AD7934-6 can have two pseudo differential pairs by setting
the MODE0 and MODE1 bits in the control register to 1 and 0,
respectively. V
IN
+ is connected to the signal source, which must
have an amplitude of V
REF
(or 2 脳 V
REF
depending on the range
chosen) to make use of the full dynamic range of the part. A dc
input is applied to the V
IN鈭?/div>
pin. The voltage applied to this input
provides an offset from ground or a pseudo ground for the V
IN
+
input.
The benefit of pseudo differential inputs is that they separate the
analog input signal ground from the ADC ground, allowing dc
common-mode voltages to be cancelled. Typically, the voltage
range for the V
IN鈭?/div>
pin while in pseudo differential mode can
extend from 鈭?.3 V to +0.7 V when V
DD
= 3 V, or from 鈭?.3 V to
+1.8V when V
DD
= 5 V. Figure 29 shows a connection diagram for
the pseudo differential mode.
ISSUE CONVST PULSE TO INITIATE A CONVERSION
ON THE SELECTED CHANNEL.
INITIATE A READ CYCLE TO READ THE DATA
FROM THE SELECTED CHANNEL.
INITIATE A WRITE CYCLE TO SELECT THE NEXT
CHANNEL TO BE CONVERTED ON BY
CHANGING THE VALUES OF BITS ADD2 TO ADD0
IN THE CONTROL REGISTER. SET SEQ0 = SEQ1 = 0.
Figure 30. Traditional Multichannel Operation Flow Chart
Using the Sequencer: Consecutive Sequence
(SEQ0 = SEQ1 = 1)
A sequence of consecutive channels can be converted beginning
with Channel 0, and ending with a final channel selected by
writing to the ADD1 and ADD0 bits in the control register. This
is done by setting the SEQ0 and SEQ1 bits in the control
register to 1. In this mode, once the control register is written
to, the next conversion is on Channel 0, then Channel 1, and so
on, until the channel selected by the address bits (ADD1 and
ADD0) is reached.
Rev. A | Page 19 of 28

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