ADAU1701
t
SIS
t
SIH
t
LOS
t
LOH
t
TS
SDATA_INx Setup
SDATA_INx Hold
OUTPUT_LRCLK Setup
OUTPUT_LRCLK Hold
OUTPUT_BCLK Falling to
OUTPUT_LRCLK Timing Skew
SDATA_OUTx Delay
SDATA_OUTx Delay
To BCLK_IN rising
From BCLK_IN rising
Slave mode
Slave mode
10
10
10
10
Preliminary Technical Data
ns
ns
ns
ns
ns
Slave mode, from OUTPUT_BCLK falling
Master mode, from OUTPUT_BCLK falling
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
400
0.6
1.3
0.6
0.6
100
300
300
300
300
Between Stop and Start
0.6
TBD
TBD
1.5 脳 1/fs
20
ns
ns
渭s
ns
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
kHz
渭s
渭s
渭s
渭s
ns
ns
ns
ns
ns
t
SODS
t
SODM
SPI PORT
t
CCPL
CCLK Pulse Width LO
t
CCPH
CCLK Pulse Width HI
t
CLS
CLATCH Setup
t
CLH
CLATCH Hold
t
CLPH
CLATCH Pulse Width HI
t
CDS
CDATA Setup
t
CDH
CDATA Hold
t
COD
COUT Delay
I
2
C PORT
f
SCL
SCL Clock Frequency
t
SCLH
SCL High
t
SCLL
SCL Low
t
SCS
Setup Time
t
SCH
Hold Time
t
DS
Data Setup Time
t
SCR
SCL Rise Time
t
SCF
SCL Fall Time
t
SDR
SDA Rise Time
t
SDF
SDA Fall Time
t
BFT
Bus-Free Time
MULTIPURPOSE PINS & RESET
t
GRT
GPIO Rise Time
t
GFT
GPIO Fall Time
t
GIL
GPIO Input Latency
t
RLPW
RESETB LO Pulse Width
To CCLK rising
From CCLK rising
To CCLK rising
From CCLK rising
From CCLK rising
Relevant for Repeated Start Condition
After this period the 1st clock is generated
Until high/low value read by core
1
All timing specifications are given for the default (I
2
S) states of the serial input control port and the serial output control ports. See
Table 45.
PLL
Table 7.
Parameter
Operating Range
Lock Time
Min
TBD
Typ
Max
TBD
20
Unit
MHz
ms
REGULATOR
1
Table 8.
Parameter
DVDD Voltage
1
Min
Typ
1.8
Max
Unit
V
Regulator specifications are calculated using an FZT953 transistor in the circuit.
Rev. PrF | Page 6 of 43