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ADAU1701

LRCLK

BCLK

SDATA

MSB

LEFT CHANNEL

LSB

1 /F

S

Preliminary Technical Data

RIGHT CHANNEL

04607-0-025

04607-0-022

MSB

LSB

Figure 34. Right-Justified Mode鈥?6 to 24 Bits per Channel

LRCLK

256 BCLKs

BCLK

32 BCLKs

DATA

SLOT 1

SLOT 2 SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

SLOT 8

LRCLK

04607-0-012

BCLK

MSB

MSB鈥?

MSB鈥?

DATA

Figure 35. TDM Mode

LRCLK

BCLK

MSB TDM

SDATA

CH

0

MSB TDM

8TH

CH

SLOT 0

32

BCLKs

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

Figure 36. TDM Mode with Pulse Word Clock

Rev. PrF | Page 36 of 43

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