音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

ADAU1701 Datasheet

  • ADAU1701

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 1329.98KB

  • 40頁

  • AD

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

ADAU1701
Aux ADC
Input Pin
20 k惟
S2
S1
10 k惟
1.8 pF
Preliminary Technical Data
1
0
DAC2 power-down
DAC3 power-down
Table 42. Aux ADC Enable Register (2084)
Register Bits
15
14:0
Function
Enable Auxiliary ADC
Reserved, set to 0
Figure 31. Auxiliary ADC input circuit
GENERAL PURPOSE INPUT/OUTPUTS
The general purpose input/output (GPIO) pins can be used as
either inputs or outputs. These pins are readable and settable
either through the control interface or directly by the SigmaDSP
core. When set as inputs, they can be used with push-button
switches or rotary encoders to control DSP program settings.
Digital outputs may be used to drive LEDs or external logic to
indicate the status of internal signals and control other devices.
Examples of this use include indicating signal overload, signal
present, and button press confirmation.
When set as outputs, these pins can typically drive 5 mA. This is
enough current to directly drive high-efficiency LEDs, which
typically need 2-4 mA. Standard LEDs require about 20 mA and
can be driven from a GPIO output with an external transistor or
buffer. When the GPIO pins are set as open-collector outputs,
they should be pulled up to a maximum voltage of 3.3 V (the
voltage on IOVDD).
Figure 31 shows the input circuit for the auxiliary ADC. Switch
S1 enables the aux ADC, and is set by bit 15 of the Aux ADC
enable register. The sampling switch, S2, operates at the audio
sampling frequency (fs), which is 48 kHz with a 12.288 MHz
crystal connected to the chip鈥檚 oscillator.
The aux ADC registers can be written to directly after bit 8 in
the DSP core control register has been set. In this mode, the
voltages on the analog inputs are not written into the registers,
but rather the data in the registers is written from the control
port. These registers take a single byte of data when in control
port write mode.
PVDD supplies the 3.3 V power for the aux ADC鈥檚 analog input.
The digital core of the aux ADC is powered with the 1.8 V
DVDD signal.
Table 40. Multi-Purpose Pin Aux ADC Mapping
Multipurpose Pin
MP0
MP1
MP2
MP3
MP4
MP5
MP6
MP7
MP8
MP9
MP10
MP11
Function
N/A
N/A
ADC1
ADC2
N/A
N/A
N/A
N/A
ADC3
ADC0
N/A
N/A
SERIAL DATA INPUT/OUTPUT PORTS
The ADAU1701鈥檚 flexible serial data input and output ports can
be set to accept or transmit data in 2-channel formats or in an
8-channel TDM stream. Data is processed in twos complement,
MSB-first format. The left channel data field always precedes
the right channel data field in the 2-channel streams. In the
TDM modes, slots 0 to 3 fall in the first half of the audio frame,
and slots 4 to 7 are in the second half of the frame. TDM mode
allows fewer multipurpose pins to be used, freeing more pins
for other functions. The serial modes are set in the serial output
and serial input control registers.
The serial data clocks need to be synchronous with the
ADAU1701鈥檚 master clock input.
The input control register allows control of clock polarity and
data input modes. The valid data formats are I
2
S , left-justified,
right-justified (24-, 20-, 18-, or 16-bit), and 8-channel TDM. In
all modes except for the right-justified modes, the serial port
will accept an arbitrary number of bits up to a limit of 24. Extra
bits will not cause an error, but they will be truncated internally.
Proper operation of the right-justified modes requires that there
be exactly 64 BCLKs per audio frame. The TDM data is input
on SDATA_IN0. The LRCLK in TDM mode can be input to the
ADAU1701 either as a 50/50 duty cycle clock or as a bit-wide
pulse.
Table 41. Auxiliary ADC & Power Control Register (2082)
Register Bits
15:10
9:8
Function
Reserved, set to 0
Aux ADC Filtering
00 = 4-bit hysteresis (12 bit level)
01 = 5-bit hysteresis (12 bit level)
01 = Hysteresis bypassed
11 = Low-pass filter bypassed
ADC power-down (both ADCs)
Voltage reference buffer power-down
Voltage reference power-down
Reserved, set to 0
DAC0 power-down
DAC1 power-down
7
6
5
4
3
2
Rev. PrF | Page 32 of 43

ADAU1701相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！