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ADAU1701 Datasheet

  • ADAU1701

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 40頁

  • AD

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Preliminary Technical Data
The following sections discuss these two options in more detail.
ADAU1701
DATA CAPTURE REGISTERS
The ADAU1701鈥檚 data capture feature allows the data at any
node in the signal processing flow to be sent to one of two
control port-readable registers. This can be used to monitor and
display information about internal signal levels or
compressor/limiter activity.
For each of the data capture registers, a capture count and a
register select must be set. The capture count is a number
between 0 and 1023 that corresponds to the program step
number where the capture will occur. The register select field
programs one of four registers in the DSP core that will be
transferred to the data capture register when the program
counter equals the capture count. The register select field
selections are shown in Table 24.
Table 24. Data Capture Control Registers (2074-2075)
Register Bits
12:2
1:0
Function
11-Bit Program Counter Address
Register Select
SAFELOAD REGISTERS
Many applications require real-time microcontroller control of
signal processing parameters, such as filter coefficients, mixer
gains, multi-channel virtualizing parameters, or dynamics
processing curves. One example is that to prevent instability
from occurring, all of the parameters of a biquad filter must be
updated at the same time. Otherwise, the filter could execute for
one or two audio frames with a mix of old and new coefficients.
This mix could cause temporary instability, leading to transients
that could take a long time to decay. To eliminate this problem,
the ADAU1701 can simultaneously load a set of five 28-bit
values to the desired parameter RAM address. Five registers are
used because a biquad filter uses five coefficients, and it is
desirable to be able to do a complete biquad update in one
transaction.
The first step in performing a safeload is writing the parameter
address to one of the Safeload Address Registers (2069 鈥?2073).
The 10-bit data word that should be written is the address to
which the safeload is being performed. After the Safeload
Address Register is set, then the 28-bit data word can be written
to the corresponding Safeload Data Register (2064 鈥?2068). The
data formats for these writes are detailed in Table 35 and Table
36. Table 23 shows how each of the five Address Registers map
to their corresponding Data Registers.
Table 23. Safeload Address & Data Register Mapping
Safeload Register
0
1
2
3
4
Safeload Address
Register
2069
2070
2071
2072
2073
Safeload Data
Register
2064
2065
2066
2067
2068
Table 25. Data Capture Output Register Select
Setting
00
01
10
11
Register
Multiplier X Input (Mult_X_input)
Multiplier Y Input (Mult_Y_input)
Multiplier-Accumulator Output (MAC_out)
Accumulator Feedback (Accum_fback)
The capture count and register select bits are set by writing to
one of the eight data capture registers at register addresses
2074: Control Port Data Capture Setup Register 0
2075: Control Port Data Capture Setup Register 1
The captured data is in 5.19 two鈥檚 complement data format. The
four LSBs are truncated from the internal 5.23 data word.
The data that must be written to set up the data capture is a
concatenation of the 11-bit program count index with the 2-bit
register select field. The capture count and register select values
that correspond to the desired point to be monitored in the
signal processing flow can be found in a file output from the
program compiler. The capture registers can be accessed by
reading from locations 2074 and 2075. The format for reading
and writing to the data capture registers can be seen in Table 33
and Table 34.
Once the address and data registers are loaded, the initiate
safeload transfer bit in the core control register should be set to
initiate the loading into RAM. Each safeload register will take
one of the 1,024 core instructions to load into the parameter
RAM. Total program lengths should be limited to 1,019 cycles
(1,024 鈭?5) to ensure that the SigmaDSP core has at least five
free cycles to perform the safeloads. It is guaranteed that the
safeload will have occurred within one LRCLK period (21 渭s at
f
s
= 48 kHz) of the initiate safeload transfer bit being set.
The safeload logic automatically sends only those safeload
registers that have been written to since the last safeload
operation. For example, if only two parameters are to be sent,
only two of the five safeload registers must be written. When
the initiate safeload transfer bit is asserted, only those two
registers are sent; the other three registers are not sent to the
RAM and can still hold old or invalid data.
Rev. PrF | Page 27 of 43

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