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ADAU1701 Datasheet

  • ADAU1701

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 40頁

  • AD

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Preliminary Technical Data
Subaddress
The 12-bit Subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
ADAU1701
format diagram for continuous-mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 28. A sample timing
diagram of a single SPI read operation is shown in Figure 29.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Bytes 0 to 2 contain the addresses and
R/W bit, and subsequent bytes carry the data.
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
SCK
SDA
START BY
MASTER
0
0
0
0
0
0
ADR
SEL
R/W
ACK. BY
ADAU1701
ACK. BY
ADAU1701
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
FRAME 2
SUBADDRESS BYTE 2
ACK. BY
ADAU1701
FRAME 3
DATA BYTE 1
ACK. BY STOP BY
ADAU1701 MASTER
Figure 22. ADAU1701 I2C Write Clocking
SCK
SDA
START BY
MASTER
ADR
SEL
R/W
ACK. BY
ADAU1701
ACK. BY
ADAU1701
FRAME 2
SUBADDRESS BYTE 1
FRAME 1
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
ACK. BY REPEATED
ADAU1701 START BY
MASTER
ADR
SEL
R/W
ACK. BY
ADAU1701
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
ACK. BY
MASTER
FRAME 5
READ DATA BYTE 1
FRAME 6
READ DATA BYTE 2
ACK. BY STOP BY
MASTER MASTER
Figure 23. ADAU1701 I
2
C Read Clocking
Rev. PrF | Page 21 of 43

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