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ADAU1701 Datasheet

  • ADAU1701

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 1329.98KB

  • 40頁

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Preliminary Technical Data
f
s
= 48 kHz and 11.2896 MHz for f
s
= 44.1 kHz. The crystal in
the oscillator circuit should be an AT-cut parallel resonance
device operating at its fundamental frequency. Figure 16 shows
the recommended external circuit for proper operation.
C1
ADAU1701
100惟
OS
CO
ADAU1701
f
s
. On power-up, a clock signal must be present on MCLK so
that the ADAU1701 can complete its initialization routine.
Table 14. PLL Modes
MCLKI Input
64 脳 f
S
256 脳 f
S
384 脳 f
S
512 脳 f
S
PLL_MODE0
0
0
1
1
PLL_MODE1
0
1
0
1
C2
MCLKI
Figure 16. Crystal oscillator circuit
The 100 惟 damping resistor on OSCO will give the oscillator a
voltage swing of approximately 2.2 V. The crystal鈥檚 shunt
capacitance should be 7 pF. Its load capacitance should be about
18 pF, although the circuit will support values up to 25 pF. The
necessary values of the load capacitors C1 and C2 can be
calculated from the crystal鈥檚 load capacitance with the equation:
The clock mode should not be changed without also resetting
the ADAU1701. If the mode is changed on the fly, a click or pop
may result on the outputs. The state of the PLL_MODEx pins
should be changed while RESETB is held low.
The PLL鈥檚 loop filter should be connected to the PLL_LF pin.
This filter, shown in Figure 17, includes three passive
components 鈥?two capacitors and a resistor. The values of these
components does not need to be exact; the tolerance can be up
to 10% for the resistor and 20% for the capacitors. The 3.3 V
signal shown in the schematic can be connected to the chip鈥檚
AVDD supply.
3.3V
C
L
=
C
1
脳
C
2
+
C
stray
C
1
+
C
2
C
stray
is the stray capacitance in the circuit and can usually be
assumed to be 2-5 pF.
OSCO should not be used to directly drive the crystal鈥檚 signal to
another IC.
If the oscillator is not being used in the design it can be
powered down to save system power. This would be done in a
case where a system master clock is already available in the
system. By default, the oscillator is powered on. The oscillator
will power down when a 1 is written to bit 2 of the Oscillator
Power-down Register (2086), as shown in Table 13.
Table 13. Oscillator Power-down Register (2086)
Register Bits
15:3
2
1:0
Function
Reserved, set to 0
Oscillator power-down
Reserved, set to 0
3.3 nF
475惟
56 nF
ADAU170
1
PLL_LF
Figure 17. PLL Loop Filter
VOLTAGE REGULATOR
The ADAU1701鈥檚 digital voltage must be set to 1.8 V. The chip
includes an on-board voltage regulator that allows it to be used
in systems where a 1.8 V supply is not available, but 3.3 V is.
The only external components needed for this are a PNP
transistor, one resistor, and bypass capacitors. Only one pin,
VDRIVE, is necessary to support the regulator.
The recommended design for the voltage regulator is shown in
Figure 18. The 10 渭F and 100 nF capacitors shown in this
schematic are recommended for bypassing, but are not
necessary for operation. Each DVDD pin should have its own
100 nF bypassing capacitor, but only one bulk capacitor (10 渭F)
is needed for all pins. Here, 3.3 V is the main system voltage.
1.8 V is generated at the transistor鈥檚 collector, which is
connected to the DVDD pins. VDRIVE is connected to the base
of the PNP transistor. If the regulator is not used in the design
VDRIVE can be tied to ground.
SETTING MASTER CLOCK/PLL MODE
The ADAU1701鈥檚 MCLK input feeds a PLL, which generates the
1024 脳 f
s
clock (49.152 MHz at f
s
= 48 kHz) to run the DSP core.
In normal operation, the input to MCLK must be one of the
following: 64 脳 f
s
, 256 脳 f
s
, 384 脳 f
s
, or 512 脳 f
s
, where f
s
is the
input sampling rate. The mode is set on PLL_MODE0, and
PLL_MODE1, according to Table 14. If the ADAU1701 is set to
receive double-rate signals (by reducing the number of program
steps/sample by a factor of 2 using the core control register),
then the master clock frequencies must be either 32 脳 f
s
, 128 脳 f
s
, 192 脳 f
s
, or 256 脳 f
s
. If the ADAU1701 is set to receive quad-
rate signals (by reducing the number of program steps/sample
by a factor of 4 using the core control register), then the master
clock frequencies must be one of 16 脳 f
s
, 64 脳 f
s
, 96 脳 f
s
, or 128 脳
Rev. PrF | Page 15 of 43

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