ADAU1701
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35
36
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PWR
A_OUT
PWR
PWR
PVDD
PLL_LF
AVDD
AGND
Preliminary Technical Data
PVDD with a 100 nF capacitor.
PVDD is the 3.3 V power supply for the PLL and the auxiliary ADC鈥檚 analog
section. This should be decoupled to PGND with a 100 nF capacitor.
PLL Loop Filter connection. Two capacitors and a resistor need to be connected
to this pin as shown in the Setting Master Clock/PLL Mode section.
AVDD is a 3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF
capacitor.
AGND is an analog ground pin. The AGND, DGND, and PGND pins can be tied
directly together in a common ground plane. AGND should be decoupled to an
AVDD pin with a 100 nF capacitor.
PLL_MODE0 and PLL_MODE1 set the output frequency of the master clock PLL.
See the Setting Master Clock/PLL Mode section for more details.
CM is the common mode reference. A 47 渭F decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the ADCs
and DACs. The capacitor鈥檚 material is not critical.
FILTD is the DAC filter decoupling pin, which should be connected to a 10 渭F
capacitor to ground. The capacitor鈥檚 material is not critical.
AGND is an analog ground pin. The AGND, DGND, and PGND pins can be tied
directly together in a common ground plane. AGND should be decoupled to an
AVDD pin with a 100 nF capacitor.
VOUT0-3 are the DAC outputs. Full-scale output voltage is 0.9 Vrms. These
outputs can be used with either active or passive output reconstruction filters.
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39
40
D_IN
D_IN
A_OUT
PLL_MODE0
PLL_MODE1
CM
41
42
A_OUT
PWR
FILTD
AGND
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44
45
46
47
48
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
PWR
VOUT3
VOUT2
VOUT1
VOUT0
FILTA
AVDD
FILTA is the ADC filter decoupling pin, which should be connected to a 10 渭F
capacitor to ground. The capacitor鈥檚 material is not critical.
AVDD is a 3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF
capacitor.
1
PWR = Power/Ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D/A_IO = digital/analog input/output
Rev. PrF | Page 12 of 43