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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 38頁

  • AD

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ADAU1702
REGULATOR
Table 6. Regulator
1
Parameter
DVDD Voltage
1
Min
1.7
Typ
1.8
Max
1.84
Unit
V
Regulator specifications are calculated using a Zetex Semiconductors FZT953 transistor in the circuit.
DIGITAL TIMING SPECIFICATIONS
Table 7. Digital Timing
1
Parameter
MASTER CLOCK
t
MP
t
MP
t
MP
t
MP
SERIAL PORT
t
BIL
t
BIH
t
LIS
t
LIH
t
SIS
t
SIH
t
LOS
t
LOH
t
TS
t
SODS
t
SODM
SPI PORT
f
CCLK
t
CCPL
t
CCPH
t
CLS
t
CLH
t
CLPH
t
CDS
t
CDH
t
COD
2
I C PORT
f
SCL
t
SCLH
t
SCLL
t
SCS
t
SCH
t
DS
t
SCR
t
SCF
t
SDR
t
SDF
t
BFT
Limit
T
MIN
T
MAX
36
48
73
291
40
40
10
10
10
10
10
10
5
40
40
6.25
80
80
0
100
80
0
80
101
400
0.6
1.3
0.6
0.6
100
300
300
300
300
0.6
244
366
488
1953
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
kHz
渭s
渭s
渭s
渭s
ns
ns
ns
ns
ns
Description
MCLK period, 512 f
S
mode.
MCLK period, 384 f
S
mode.
MCLK period, 256 f
S
mode.
MCLK period, 64 f
S
mode.
INPUT_BCLK low pulse width.
INPUT_BCLK high pulse width.
INPUT_LRCLK setup. Time to INPUT_BCLK rising.
INPUT_LRCLK hold. Time from INPUT_BCLK rising.
SDATA_INx setup. Time to BCLK_IN rising.
SDATA_INx hold. Time from BCLK_IN rising.
OUTPUT_LRCLK setup in slave mode.
OUTPUT_LRCLK hold in slave mode.
OUTPUT_BCLK falling to OUTPUT_LRCLK timing skew.
SDATA_OUTx delay. Time from OUTPUT_BCLK falling in slave mode.
SDATA_OUTx delay. Time from OUTPUT_BCLK falling in master mode.
CCLK frequency.
CCLK pulse width low.
CCLK pulse width high.
CLATCH setup. Time to CCLK rising.
CLATCH hold. Time from CCLK rising.
CLATCH pulse width high.
CDATA setup. Time to CCLK rising.
CDATA hold. Time from CCLK rising.
COUT delay. Time from CCLK falling.
SCL frequency.
SCL high.
SCL low.
Setup time, relevant for repeated start condition.
Hold time. After this period, the first clock is generated.
Data setup time.
SCL rise time.
SCL fall time.
SDA rise time.
SDA fall time.
Bus-free time. Time between stop and start.
Rev. 0 | Page 5 of 52

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