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ADAU1702

LRCLK

BCLK

05798-018

LEFT CHANNEL

RIGHT CHANNEL

SDATA

MSB

LSB

1/F

S

MSB

LSB

Figure 31. I

2

S Mode鈥?6 Bits to 24 Bits per Channel

LRCLK

BCLK

SDATA

MSB

LEFT CHANNEL

LSB

1/F

S

MSB

RIGHT CHANNEL

LSB

Figure 32. Left-Justified Mode鈥?6 Bits to 24 Bits per Channel

LRCLK

BCLK

SDATA

MSB

LEFT CHANNEL

LSB

1/F

S

RIGHT CHANNEL

Figure 33. Right-Justified Mode鈥?6 Bits to 24 Bits per Channel

LRCLK

256 BCLKs

BCLK

32 BCLKs

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

SLOT 8

DATA

LRCLK

05798-021

BCLK

MSB

MSB鈥?

MSB鈥?

DATA

Figure 34. TDM Mode

LRCLK

BCLK

MSB TDM

SDATA

CH

0

MSB TDM

8TH

CH

SLOT 0

32

BCLKs

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SLOT 6

SLOT 7

05798-022

Figure 35. TDM Mode with Pulse Word Clock

Rev. 0 | Page 46 of 52

05798-020

MSB

LSB

05798-019

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