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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 694.40KB

  • 38頁

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ADAU1702
DIGITAL INPUT/OUTPUT
Table 2.
Parameter
Input Voltage, High (V
IH
)
Input Voltage, Low (V
IL
)
Input Leakage, High (I
IH
)
Input Leakage, Low (I
IL
)
Bidirectional Pin Pull-Up Current, Low
MCLKI Input Leakage, High (I
IH
)
MCLKI Input Leakage, Low (I
IL
)
High Level Output Voltage (V
OH
), I
OH
= 2 mA
Low Level Output Voltage (V
OL
), I
OL
= 2 mA
Input Capacitance
GPIO Output Drive
Min
2.0
Typ
Max
IOVDD
0.8
1
1
3
3
2.0
0.8
5
2
Unit
V
V
渭A
渭A
渭A
渭A
渭A
V
V
pF
mA
Comments
Excluding MCLKI
Excluding MCLKI and bidirectional pins
150
POWER
Table 3.
Parameter
SUPPLY VOLTAGE
Analog Voltage
Digital Voltage
PLL Voltage
IOVDD Voltage
SUPPLY CURRENT
Analog Current (AVDD and PVDD)
Digital Current (DVDD)
Analog Current, Reset
Digital Current, Reset
DISSIPATION
Operation (AVDD, DVDD, PVDD)
2
Reset, All Supplies
POWER SUPPLY REJECTION RATIO (PSRR)
1 kHz, 200 mV
P-P
Signal at AVDD
1
Min
Typ
3.3
1.8
3.3
3.3
50
40
35
1.5
286.5
118
50
Max
1
Unit
V
V
V
V
85
60
55
4.5
mA
mA
mA
mA
mW
mW
dB
Maximum specifications are measured across a temperature range of
鈭?0擄C
to +130擄C (case) and across a DVDD range of 1.62 V to 1.98 V and an AVDD range of 2.97 V
to 3.63 V.
2
Power dissipation does not include IOVDD power because the current drawn from this supply is dependent on the loads at the digital output pins.
TEMPERATURE RANGE
Table 4.
Parameter
Functionality Guaranteed
Min
0擄C
Typ
Max
70擄C
Unit
擄C ambient
PLL AND OSCILLATOR
Table 5.
Parameter
PLL Operating Range
Min
MCLK_Nom 鈭?20%
Typ
Max
MCLK_Nom + 20%
Unit
MHz
Comments
MCLK_Nom is the nominal input in a
given mode (for example, 12.288 MHz in
256 脳 f
S
mode with a f
s
of 48 kHz)
PLL Lock Time
Crystal Oscillator g
m
(Transconductance)
20
78
ms
mmho
Rev. 0 | Page 4 of 52

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