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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 694.40KB

  • 38頁

  • AD

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ADAU1702
2078 (0x081E)鈥擲ERIAL OUTPUT CONTROL REGISTER
Table 48.
D15
0
D14
0
D13
OLRP
D12
OBP
D11
M/S
D10
OBF1
D9
OBF0
D8
OLF1
D7
OLF0
D6
FST
D5
TDM
D4
MSB2
D3
MSB1
D2
MSB0
D1
OWL1
D0
OWL0
Default
0x0000
Table 49.
Bit Name
OLRP
OUTPUT_LRCLK Polarity
OBP
OUTPUT_BCLK Polarity
M/S
Master/Slave
OBF [1:0]
OUTPUT_BCLK Freq
(Master Mode Only)
Description
When this bit is set to 0, the left-channel data is clocked when OUTPUT_LRCLK is low and the right-channel
data is clocked when OUTPUT_LRCLK is high. When this bit is set to 1, the right-channel data is clocked when
OUTPUT_LRCLK is low and the left-channel data is clocked when OUTPUT_LRCLK is high.
This bit controls on which edge of the bit clock the output data is clocked. Data changes on the falling edge
of OUTPUT_BCLK when this bit is set to 0 and on the rising edge when this bit is set to 1.
This bit sets whether the output port is a clock master or slave. The default setting is slave; on power-up, the
OUTPUT_BCLK and OUTPUT_LRCLK pins are set as inputs until this bit is set to 1, at which time they become
clock outputs.
When the output port is being used as a clock master, these bits set the frequency of the output bit clock,
which is divided down from an internal 1024 脳 f
S
clock (49.152 MHz for a f
S
of 48 kHz).
OBF [1:0]
Setting
00
Internal clock/16
01
Internal clock/8
10
Internal clock/4
11
Internal clock/2
When the output port is used as a clock master, these bits set the frequency of the output word clock on the
OUTPUT_LRCLK pins, which is divided down from an internal 1024 脳 f
S
clock (49.152 MHz for a f
S
of 48 kHz).
OLF [1:0]
Setting
00
Internal clock/1024
01
Internal clock/512
10
Internal clock/256
11
Reserved
This bit sets the type of signal on the OUTPUT_LRCLK pins. When this bit is set to 0, the signal is a word clock
with a 50% duty cycle; when this bit is set to 1, the signal is a pulse with a duration of one bit clock at the
beginning of the data frame.
Setting this bit to 1 changes the output port from four serial stereo outputs to a single 8-channel TDM output
stream on the SDATA_OUT0 pin (MP6).
These three bits set the position of the MSB of data with respect to the LRCLK edge. The data output of the
ADAU1702 is always MSB first.
MSB [2:0]
Setting
000
Delay by 1
001
Delay by 0
010
Delay by 8
011
Delay by 12
100
Delay by 16
101
Reserved
111
Reserved
These bits set the word length of the output data-word. All bits following the LSB are set to 0.
OWL [1:0]
Setting
00
24 bits
01
20 bits
10
16 bits
11
Reserved
OLF [1:0]
OUTPUT_LRCLK Freq
(Master Mode Only)
FST
Frame Sync Type
TDM
TDM Enable
MSB [2:0]
MSB Position
OWL [1:0]
Output Word Length
Rev. 0 | Page 39 of 52

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