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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 38頁(yè)

  • AD

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ADAU1702
Pin No.
39
40
Mnemonic
PLL_MODE1
CM
Type
1
D_IN
A_OUT
Page No.
17
Description
of the master clock PLL. See the Setting Master Clock/PLL Mode section for
more details.
1.5 V Common-Mode Reference. A 47 渭F decoupling capacitor should be
connected between this pin and ground to reduce crosstalk between the
ADCs and DACs. The material of the capacitors is not critical. This pin can be
used to bias external analog circuits, as long as they are not drawing current
from CM (for example, the noninverting input of an op amp).
DAC Filter Decoupling Pin. Should be connected to a 10 渭F capacitor to ground.
The capacitor material is not critical. The voltage on the FILTD is 1.5 V.
VOUT0 to VOUT3 are the DAC Outputs. Full-scale output voltage is 0.9 V
rms
. These
outputs can be used with either active or passive output reconstruction filters.
41
43
44
45
46
47
1
FILTD
VOUT3
VOUT2
VOUT1
VOUT0
FILTA
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
A_OUT
20
20
20
20
ADC Filter Decoupling Pin. Should be connected to a 10 渭F capacitor to ground.
The capacitor material is not critical. The voltage on the FILTA pin is 1.5 V.
PWR = power/ground, A_IN = analog input, D_IN = digital input, A_OUT = analog output, D_IO = digital input/output, D_IO/A_IO = digital input/output or analog
input/output.
Rev. 0 | Page 12 of 52

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