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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 38頁

  • AD

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ADAU1702
Pin No.
14
15
16
17
18
Mnemonic
MP7
MP6
MP10
VDRIVE
IOVDD
Type
1
D_IO
D_IO
D_IO
A_OUT
PWR
Page No.
44
44
44
5
Description
Multipurpose GPIO or Serial Output Port Data 1 (SDATA_OUT1).
Multipurpose GPIO, Serial Output Port Data 0, or TDM Data Output
(SDATA_OUT0).
Multipurpose GPIO or Serial Output Port LRCLK (OUTPUT_LRCLK).
Drive for 1.8 V Regulator. The base of the voltage regulator external PNP
transistor is driven from VDRIVE.
Supply for Input and Output Pins. The voltage on this pin sets the highest
input voltage that should be seen on the digital input pins. This pin is also
the supply for the digital output signals on the control port and MP pins.
IOVDD should always be set to 3.3 V. The current draw of this pin is variable
because it is dependent on the loads of the digital outputs.
Multipurpose GPIO or Serial Output Port BCLK (OUTPUT_BCLK).
ADDR1: I
2
C Address 1. In combination with ADDR0, this sets the I
2
C address
of the IC so that four ADAU1702s can be used on the same I
2
C bus.
CDATA: SPI Data Input.
WB: EEPROM Writeback Trigger. A rising (default) or falling (if set in the
EEPROM messages) edge on this pin triggers a writeback of the interface
registers to the external EEPROM. This function can be used to save
parameter data on power-down.
CLATCH: SPI Latch Signal. Must go low at the beginning of an SPI transaction
and high at the end of a transaction. Each SPI transaction can take a different
number of CCLKs to complete, depending on the address and read/write bit
that are sent at the beginning of the SPI transaction.
WP: Self-Boot EEPROM Write Protect. This pin is an open-collector output
when in self-boot mode. The ADAU1702 pulls this low to prohibit writes to
an external EEPROM. This pin should be pulled high to 3.3 V.
SDA: I
2
C Data. This pin is a bidirectional open-collector. The line connected
to this pin should have a 2.2 k惟 pull-up resistor.
COUT: This SPI data output is used for reading back registers and memory
locations. It is three-stated when an SPI read is not active.
SCL: I
2
C Clock. This pin is always an open-collector input when in I
2
C control
mode. In self-boot mode, this pin is an open-collector output (I
2
C master).
The line connected to this pin should have a 2.2 k惟 pull-up resistor.
CCLK: SPI Clock. This pin can either run continuously or be gated off in
between SPI transactions.
Multipurpose GPIO, Serial Output Port Data 3 (SDATA_OUT3), or Auxiliary
ADC Input 0.
Multipurpose GPIO, Serial Output Port Data 2 (SDATA_OUT2), or Auxiliary
ADC Input 3.
Multipurpose GPIO, Serial Input Port Data 3 (SDATA_IN3), or Auxiliary
ADC Input 2.
Multipurpose GPIO, Serial Input Port Data 2 (SDATA_IN2), or Auxiliary
ADC Input 1.
Reserved. Tie to ground, either directly or through a pull-down resistor.
Crystal Oscillator Circuit Output. A 100 惟 damping resistor should be
connected between this pin and the crystal. This output should not be used
to directly drive a clock to another IC. If the crystal oscillator is not used, this
pin can be left disconnected.
Master Clock Input. MCLKI can either be connected to a 3.3 V clock signal or
can be the input from the crystal oscillator circuit.
PLL Ground Pin. The AGND, DGND, and PGND pins can be tied directly
together in a common ground plane. PGND should be decoupled to PVDD
with a 100 nF capacitor.
3.3 V Power Supply for the PLL and the Auxiliary ADC Analog Section. This
should be decoupled to PGND with a 100 nF capacitor.
PLL Loop Filter Connection. Two capacitors and a resistor need to be connected
to this pin, as shown in the Setting Master Clock/PLL Mode section.
3.3 V Analog Supply. This should be decoupled to AGND with a 100 nF capacitor.
PLL Mode Setting. PLL_MODE0 and PLL_MODE1 set the output frequency
Rev. 0 | Page 11 of 52
19
20
MP11
ADDR1/CDATA/WB
D_IO
D_IN
44
22, 24, 26
21
CLATCH/WP
D_IO
24, 26
22
SDA/COUT
D_IO
21, 24
23
SCL/CCLK
D_IO
21, 24
26
27
28
29
30
31
MP9
MP8
MP3
MP2
RSVD
OSCO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
D_IO/A_IO
X
D_OUT
44
44
44
44
17
32
33
MCLKI
PGND
D_IN
PWR
17
34
35
36, 48
38
PVDD
PLL_LF
AVDD
PLL_MODE0
PWR
A_OUT
PWR
D_IN
17
17

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