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ADAU1702 Datasheet

  • ADAU1702

  • SigmaDSP? 28/56-Bit Audio Processor with 2ADC/4DAC

  • 38頁

  • AD

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ADAU1702
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PLL_MODE1
PLL_MODE0
VOUT0
VOUT1
VOUT2
VOUT3
AGND
AGND
FILTA
FILTD
AVDD
CM
48 47 46 45 44 43 42 41 40 39 38 37
AGND
ADC1
ADC_RES
ADC0
RESET
1
2
3
4
5
PIN 1
INDICATOR
36
35
34
33
32
31
30
29
28
27
26
25
AVDD
PLL_LF
PVDD
PGND
MCLKI
OSCO
RSVD
MP2
MP3
MP8
MP9
DGND
ADAU1702
TOP VIEW
(Not to Scale)
SELFBOOT
6
ADDR0
7
MP4
MP5
8
9
MP1
10
MP0
11
DGND
12
13 14 15 16 17 18 19 20 21 22 23 24
IOVDD
CLATCH/WP
SCL/CCLK
MP7
MP6
VDRIVE
MP10
MP11
DVDD
ADDR1/CDATA/WB
SDA/COUT
DVDD
Figure 7. 48-Lead LQFP Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1, 37, 42
Mnemonic
AGND
Type
1
PWR
Page No.
Description
Analog Ground Pin. The AGND, DGND, and PGND pins can be tied directly
together in a common ground plane. AGND should be decoupled to an
AVDD pin with a 100 nF capacitor.
Analog Audio Input 1. Full-scale 100 渭A
rms
input. Current input allows input
voltage level to be scaled with an external resistor. An 18 k惟 resistor gives a
2 V
rms
full-scale input.
ADC Reference Current. The full-scale current of the ADCs can be set with an
external 18 k惟 resistor connected between this pin and ground.
Analog Audio Input 0. Full-scale 100 渭A
rms
input. Current input allows input
voltage level to be scaled with an external resistor. An 18 k惟 resistor gives a
2 V
rms
full-scale input.
Active Low Reset Input. Reset is triggered on a high-to-low edge and the
ADAU1702 exits reset on a low-to-high edge. For more information about
initialization, see the Power-Up Sequence section.
Enable/Disable Self-Boot. SELFBOOT selects control port (low) or self-boot
(high). Setting this pin high initiates a self-boot operation when the ADAU1702
is brought out of reset. This pin can be tied directly to the control voltage or
pulled up/down with a resistor.
I
2
C and SPI Address 0. In combination with ADDR1, this pin allows up to four
ADAU1702s to be used on the same I
2
C bus and up to two ICs to be used
with a common SPI CLATCH signal.
Multipurpose GPIO or Serial Input Port LRCLK (INPUT_LRCLK).
Multipurpose GPIO or Serial Input Port BCLK (INPUT_BCLK).
Multipurpose GPIO or Serial Input Port Data 1 (SDATA_IN0).
Multipurpose GPIO or Serial Input Port Data 0 (SDATA_IN1).
Digital Ground Pin. The AGND, DGND, and PGND pins can be tied directly
together in a common ground plane. DGND should be decoupled to a
DVDD pin with a 100 nF capacitor.
1.8 V Digital Supply. This can be supplied either externally or generated
from a 3.3 V supply with the on-board 1.8 V regulator. DVDD should be
decoupled to DGND with a 100 nF capacitor.
Rev. 0 | Page 10 of 52
2
ADC1
A_IN
19
3
4
ADC_RES
ADC0
A_IN
A_IN
19
19
5
RESET
D_IN
6
SELFBOOT
D_IN
26
7
ADDR0
D_IN
22
8
9
10
11
12, 25
MP4
MP5
MP1
MP0
DGND
D_IO
D_IO
D_IO
D_IO
PWR
44
44
44
44
13, 24
DVDD
PWR
05798-002

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