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ADM3483 Datasheet

  • ADM3483

  • 3.3 V Slew Rate Limited, Half and Full Duplex,RS-485/RS-422 ...

  • 17頁

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ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TEST CIRCUITS
A/Y
R
L
/2
V
OD
05524-003
C
L
D
GENERATOR
1
V
OC
R
L
=
OUT
60鈩?/div>
50鈩?/div>
V
CC
C
L
= 15pF
2
05524-036
R
L
/2
B/Z
1
PPR = 250kHz, 50% DUTY CYCLE,
t
鈮?/div>
6.0ns, Z = 50鈩?
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
Figure 7. Differential Output Voltage
and Common-Mode Voltage Drivers
Figure 10. Driver Differential Output Delay and Transition Times
V
OM
R
L
= 27鈩?/div>
S1
D
OUT
C
L
= 15pF
2
V
CC
05524-004
375鈩?/div>
D
V
CC
V
OD
R
L
V
CM
=
鈥?V TO +12V
GENERATOR
1
50鈩?/div>
375鈩?/div>
V
OM
=
V
OH
+ V
OL
2
鈮?/div>
1.5V
05524-037
1
PPR = 250kHz, 50% DUTY CYCLE,
t
鈮?/div>
6.0ns, Z = 50鈩?
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
Figure 8. Differential Output Voltage Drivers
with Varying Common-Mode Voltage
Figure 11. Driver Propagation Delays
S1
0V OR 3V
D
C
L
= 50pF
2
V
ID
R
OUT
R
L
= 110鈩?/div>
GENERATOR
1
0
05524-005
50鈩?/div>
V
OM
=
V
OH
+ V
OL
2
鈮?/div>
1.5V
05524-038
V
OL
I
OL
(+)
V
OH
I
OH
(鈥?
1
PPR = 250kHz, 50% DUTY CYCLE,
t
鈮?/div>
6.0ns, Z = 50鈩?
R
O
2
C INCLUDES PROBE AND STRAY CAPACITANCE.
L
Figure 9. CMOS Output Voltage High and
CMOS Output Voltage Low Receivers
Figure 12. Driver Enable and Disable Times (t
PZH
, t
PSH
, t
PHZ
)
Rev. B | Page 9 of 20

ADM3483 PDF文件相關型號

ADM3485,ADM3488,ADM3490

ADM3483相關型號PDF文件下載

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  • 英文版
    3.3 V Slew Rate Limited, Half and Full Duplex,RS-485/RS-422 ...
    AD
  • 英文版
    3.3 V Slew Rate Limited, Half and Full Duplex,RS-485/RS-422 ...
    AD
  • 英文版
    3.3 V Slew Rate Limited, Half and Full Duplex,RS-485/RS-422 ...
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