SLUS593B 鈭?DECEMBER 2003 鈭?REVISED APRIL 2004
TPS40054
TPS40055
TPS40057
DESIGN EXAMPLE
The poles and zeros for a type III network are described in equations (25) and (26).
f
Z2
+
f
P2
+
f
C
+
f
P1
+
f
Z1
+
2p
2p
2p
2p
2p
1
R1
1
R3
1
R1
1
R2
1
R2
C2
C2
C1
G
C3
C3
N
C3
+
N
R3
+
2p
2p
1
100 kW
1
330 pF
2p
4.93 kHz
73.3 kHz
1
100 kW
3.29
20 kHz
1
22 pF
1
97.6 kW
+
323 pF, choose 330 pF
+
6.55 kW, choose 6.49 kW
+
24.2 pF, choose 22 pF
(75)
(76)
(77)
(78)
(79)
N
C2
+
N
R2
+
N
C1
+
2p
2p
73.3 kHz
+
98.2 kW, choose 97.6 kW
+
331 pF, choose 330 pF
4.93 kHz
Calculate the value of R
BIAS
from equation (23) with R1 = 100 k鈩?
R
BIAS
+
0.7 V R1
+
0.7 V 100kW
+
26.9 kW, choose 26.7 kW
V
O
*
0.7 V
3.3 V
*
0.7 V
(80)
CALCULATING THE BOOST AND BP10V BYPASS CAPACITANCE
The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass cap. The BOOST capacitance for the Si7860DP, allowing for a 0.5 voltage droop
on the BOOST pin from equation (29) is:
C
BOOST
+
Q
g
+
18 nC
+
36 nF
0.5 V
DV
Q
gHS
)
Q
gSR
DV
(81)
and the BP10V capacitance from (32) is
C
BP(10 V)
+
+
2
Q
g
+
36 nC
+
72 nF
0.5 V
DV
(82)
For this application, a 0.1-碌F capacitor is used for the BOOST bypass capacitor and a 1.0-碌F capacitor is used
for the BP10V bypass.
DESIGN EXAMPLE SUMMARY
Figure 15 shows component selection for the 10-V to 24-V to 3.3-V at 8 A dc-to-dc converter specified in the
design example. For an 8-V input application, it may be necessary to add a Schottky diode from BP10 to BOOST
to get sufficient gate drive for the upper MOSFET. As seen in Figure 7, the BP10 output is about 6 V with the
input at 8 V so the upper MOSFET gate drive may be less than 5 V.
A schottky diode is shown connected across the synchronous rectifier MOSFET as an optional device that may
be required if the layout causes excessive negative SW node voltage, greater than or equal to 2 V.
30
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