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TPS40055 Datasheet

  • TPS40055

  • 寬輸入 (8V-40V) 最高頻率 1MHz 的同步降壓控制器，具有輸出驅(qū)動...

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  • TI

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SLUS593B 鈭?DECEMBER 2003 鈭?REVISED APRIL 2004
TPS40054
TPS40055
TPS40057
LAYOUT CONSIDERATIONS
THE POWERPADt PACKAGE
The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package dimensions of the circuit board pad area are 5 mm x 3.4 mm
[2]
. The dimensions of the package
pad are shown in Figure 14.
Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper
is plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with
a diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to
PowerPAD Thermally
Enhanced Package
[2]
and the mechanical illustration at the end of this document for more information on the
PowerPAD package.
5,10 mm
4,90 mm
Thermal Pad
2,46 mm
1,86 mm
4,50 mm 6,60 mm
4,30 mm 6,20 mm
1
2,31 mm
1,75 mm
8
Figure 15. PowerPAD Dimensions
MOSFET PACKAGING
MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions.
In general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance
(胃
JA
) and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends
on proper layout and thermal management. The
胃
JA
specified in the MOSFET data sheet refers to a given
copper area and thickness. In most cases, a lowest thermal impedance of 40擄C/W requires one square inch
of 2-ounce copper on a G鈭?0/FR鈭? board. Lower thermal impedances can be achieved at the expense of board
area. Please refer to the selected MOSFET鈥檚 data sheet for more information regarding proper mounting.
24
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