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TPS40055 Datasheet

  • TPS40055

  • 寬輸入 (8V-40V) 最高頻率 1MHz 的同步降壓控制器，具有輸出驅(qū)動...

  • 34頁

  • TI

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SLUS593B 鈭?DECEMBER 2003 鈭?REVISED APRIL 2004
TPS40054
TPS40055
TPS40057
APPLICATION INFORMATION
The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, R
KFF
needs to be adjusted for the higher switching
frequency. In order to specify the correct value for R
KFF
at the synchronizing frequency, calculate a 鈥檇ummy鈥?/div>
value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT
in the design.
R
T(dummy)
+
1
17.82
*
17
kW
(17)
f
SYNC
10
*6
Use the value of R
T(dummy)
to calculate the value for R
KFF
.
R
KFF
+
V
IN(min)
*
3.5 V
58.14
R
T(dummy)
)
1340
W
(18)
This value of R
KFF
ensures that UVLO is not engaged when operating at the synchronization frequency.
D
R
T(dummy)
is in k鈩?/div>
LOOP COMPENSATION
Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS4005x
uses voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must be
included. The modulator gain is described in Figure 9, with V
IN
being the minimum input voltage required to
cause the ramp excursion to cover the entire switching period as described in equation (19).
A
MOD
+
V
IN
V
S
or
A
MOD(dB)
+
20
log
V
IN
V
S
(19)
Duty dycle, D, varies from 0 to 1 as the control voltage, V
C
, varies from the minimum ramp voltage to the
maximum ramp voltage, V
S
. Also, for a synchronous buck converter, D = V
O
/ V
IN
. To get the control voltage
to output voltage modulator gain in terms of the input voltage and ramp voltage,
D
+
V
V
O
+
C
V
IN
V
S
or
V
O
V
+
IN
V
C
V
S
(20)
Calculate the Poles and Zeros
For a buck converter using voltage mode control there is a double pole due to the output L-C
O
. The double pole
is located at the frequency calculated in equation (21).
f
LC
+
2p
1
L
(Hertz)
C
O
(21)
There is also a zero created by the output capacitance, C
O
, and its associated ESR. The ESR zero is located
at the frequency calculated in equation (22).
f
Z
+
2p
1
ESR
C
O
(Hertz)
(22)
Calculate the value of R
BIAS
to set the output voltage, V
OUT
.
R
BIAS
+
0.7 R1
W
V
OUT
*
0.7
(23)
www.ti.com
17

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