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TPS40055 Datasheet

  • TPS40055

  • 寬輸入 (8V-40V) 最高頻率 1MHz 的同步降壓控制器，具有輸出驅(qū)動(dòng)...

  • 634.57KB

  • 34頁

  • TI

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SLUS593B 鈭?DECEMBER 2003 鈭?REVISED APRIL 2004
TPS40054
TPS40055
TPS40057
APPLICATION INFORMATION
Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp duration
is longer than the clock cycle before an undervoltage condition is declared. (See Figure 4).
UVLO Threshold
VIN
Clock
PWM RAMP
1 2 3 4 5 6 7
PowerGood
1 2
1 2 3 4 5 6 7
UDG鈭?2132
Figure 4. Undervoltage Lockout Operation
The tolerance on the UVLO set point also affects the maximum duty cycle achievable. If the UVLO starts the
device at 10% below the nominal start up voltage, the maximum duty cycle is reduced approximately 10% at
the nominal start up voltage.
The impedance of the input voltage can cause the input voltage, at the controller, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point. With R
T
chosen to select the operating frequency and R
KFF
chosen
to select the start鈭抲p voltage, the approximate amount of hysteresis voltage is shown in Figure 5.
UNDERVOLTAGE LOCKOUT THRESHOLD
vs
HYSTERESIS
1.2
1.0
VUVLO 鈭?Hysteresis 鈭?V
0.8
0.6
0.4
0.2
0
10
15
20
25
30
35
40
VUVLO 鈭?Undevoltage Lockout Threshold 鈭?V
Figure 5.
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