TPS40007
TPS40009
SLUS589A鈭?NOVEMBER 2003 鈭?REVISED MAY 2004
ELECTRICAL CHARACTERISTICS
temperature range, T
A
= 鈭?0_C to 85_C, V
DD
= 5.0 V, T
A
= T
J
; all parameters measured at zero power dissipation
(unless otherwise noted)
PARAMETER
OUTPUT DRIVER
RHDHI
RHDLO
RLDHI
RLDLO
tRLD
tFLD
tRHD
tFHD
VSWP
TLDHD
THDLD
HDRV pull-up resistance
HDRV pull-down resistance
LDRV pull-up resistance
LDRV pull-down resistance
LDRV rise time
LDRV fall time
HDRV rise time
HDRV fall time
Sense threshold to modulate delay time
Maximum delay modulation range time
Predictive counter delay time per bit
Maximum delay modulation range
Predictive counter delay time per bit
SHUTDOWN
VSD
VEN
ISS
VSS
Shutdown threshold voltage
Device active threshold voltage
Soft-start source current
Soft-start voltage to begin VOUT start
VDD = 3.3 V
VDD = 5 V
Outputs OFF
Outputs OFF
0.21
0.25
2.0
0.35
0.26
0.29
3.7
0.65
50
35
0.31
0.35
5.4
0.95
100
70
V
LDRV OFF 鈭?to 鈭?HDRV ON
LDRV OFF 鈭?to 鈭?HDRV ON
HDRV OFF 鈭?to 鈭?LDRV ON
HDRV OFF 鈭?to 鈭?LDRV ON
45
2.8
50
3.0
CLOAD = 1 nF
VBOOT鈭扸SW = 3.3 V,
ISOURCE = 鈭?00 mA
VBOOT 鈭?VSW = 3.3 V,
ISINK = 100 mA
VDD = 3.3 V,
VDD = 3.3 V,
ISOURCE = 鈭?00 mA
ISINK = 100 mA
3
1.5
3
1.0
15
10
15
10
鈭?50
70
4.3
80
4.8
95
6.2
110
6.6
ns
5.5
3
5.5
2.0
35
25
35
25
mV
ns
鈩?/div>
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PREDICTIVE DELAY
SOFTSTART
碌A(chǔ)
V
BOOTSTRAP
RBOOT
Bootstrap switch resistance
鈩?/div>
VOUT PRE-BIAS
Recommended VOUT pre-bias level as
% of final regulation(1)(4)
SW NODE
ISW
Leakage current in shutdown
THERMAL SHUTDOWN
tSD
Shutdown temperature(1)
Restart from thermal shutdown(1)
(1)
(2)
(3)
(4)
Ensured by design. Not production tested.
FB percent of 700 mV
90%
2
165
鈭?5
碌A(chǔ)
擄C
Derate the maximum duty cycle by 3% for VDD < 3 V.
Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
Prebiased output greater than 90% of final regulation may lead to sinking current from the prebias output.
4
www.ti.com
prev
next