鈮?/div>
5.00 V
VPEAK 鈭?VVALLEY
250
500
0.80
0.24
300
600
0.93
0.31
350
700
1.07
0.44
V
kHz
VBOOT 鈭?VSW
SS/SD = 0 V,
FB = 0.8 V
No load at HDRV/LDRV
1.95
80
Outputs off
2.25
0.25
1.4
1.5
2.05
150
5.5
6
0.45
2.0
4.0
2.15
220
V
mV
mA
V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
AOL
Open loop gain
SHORT CIRCUIT CURRENT PROTECTION
ISINK
ISINK
VOS
VILIM
tON
ILIM sink current
ILIM sink current
Offset voltage SW vs ILIM(1)
Input voltage range
Minimum HDRV pulse time in overcurrent
SW leading edge blanking pulse in over-
current detection(1)
tSS
Soft-start capacitor cycles as fault timer(1)
(1) Ensured by design. Not production tested.
(2) Derate the maximum duty cycle by 3% for VDD < 3 V
(3) Operating at PWM on-times of less than 100 ns could lead to overlap between HDRV and LDRV pulses.
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