音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

TPS40074 Datasheet

  • TPS40074

  • 具有電壓前饋的中等范圍輸入同步降壓控制器

  • 348.00KB

  • 38頁

  • TI

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

TPS40074
SLUS617 鈥?APRIL 2005
www.ti.com
Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
BOOST
NO.
11
I/O
DESCRIPTION
The BOOST voltage is 8-V greater than the input voltage. The peak voltage on BOOST is equal to the SW node
voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal
bootstrap diode or 300 mV for an external schottkey diode. The voltage differential between this pin and SW is the
available drive voltage for the high-side FET.
Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the
FB pin to compensate the overall loop. This pin is internally clamped to a 3.4-V maximum output drive capability
for quicker recovery from a saturated feedback loop situation.
8-V regulator output used for the gate drive of the N-channel synchronous rectifier and as the supply for charging
the bootstrap capacitor. This pin should be bypassed to ground with a 1.0-碌F ceramic capacitor.
Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.
Ground reference for the device.
Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).
Short circuit protection programming pin. This pin is used to set the overcurrent threshold. An internal current sink
from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage
on this pin is compared to the voltage drop (V
VDD
-V
SW
) across the high side N-channel MOSFET during
conduction. Just prior to the beginning of a switching cycle this pin is pulled to approximately V
VDD
/2 and released
when SW is within 2 V of V
VDD
or after a timeout (the precondition time) - whichever occurs first. Placing a
capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch on time,
effectively programming the ILIM blanking time. See
Applications Information
section.
A resistor is connected from this pin to VDD programs the amount of input voltage feed-forward. The current fed
into this pin is used to control the slope of the PWM ramp and program undervoltage lockout. Nominal voltage at
this pin is maintained at 400 mV.
Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to PGND (MOSFET
off).
4.2-V reference used for internal device logic and analog functions. This pin should be bypassed to GND with a
0.1-碌F ceramic capacitor. External loads less than 1 mA and electrically quiet may be applied.
This is an open drain output that pulls to ground when soft start is active, or when the FB pin is outside a 鹵10%
band around the 700 mV reference voltage.
Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the
lower MOSFET(s).
I
I
I
O
A resistor is connected from this pin to GND to set the switching frequency.
Noninverting input of the remote voltage sense amplifier.
Inverting input of the remote voltage sense amplifier.
Output of the remote voltage sense amplifier.
Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The
capacitor is charged with an internal current source of 12 碌A(chǔ). The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V
less that that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the
SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is below the
internal offset voltage of 1 V (300 mV minimum ensured), the resulting output voltage is zero. Also provides timing
for fault recovery attempts.
This pin is connected to the switched node of the converter and used for overcurrent sensing as well as gate drive
timing. This pin is also the return path from the high-side FET for the floating high-side FET driver.
Logic input for pulse train to synchronize oscillator.
Supply voltage for the device.
I
COMP
DBP
FB
GND
HDRV
6
9
5
3
12
O
O
I
-
O
ILIM
14
I
KFF
LDRV
LVBP
PGD
PGND
RT
SA+
SA-
SAO
15
8
17
18
7
16
20
1
2
I
O
O
O
SS
4
I
SW
SYNC
VDD
10
19
13
I
I
I
6

TPS40074 PDF文件相關(guān)型號

TPS40100,TPS40222,TPS5130

TPS40074相關(guān)型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！